公开(公告)号：US5315548A

公开(公告)日：1994-05-24

申请号：US900368

申请日：1992-06-18

Applicant: Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

Inventor： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC: G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C8/12 ,  G11C7/10

Abstract: Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

Abstract translation: 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US5226139A

公开(公告)日：1993-07-06

申请号：US637872

申请日：1991-01-08

Applicant: Kazuyasu Fujishima ,  Yoshio Matsuda ,  Hideto Hidaka ,  Mikio Asakura

Inventor： Kazuyasu Fujishima ,  Yoshio Matsuda ,  Hideto Hidaka ,  Mikio Asakura

IPC: G06F9/38 ,  G06F12/08 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/41

CPC classification number: G06F9/3824 ,  G06F12/0893 ,  G11C11/408 ,  G11C11/4096

Abstract: A semiconductor memory device with a built-in cache memory comprises a memory cell array (1). The memory cell array (1) is divided into a plurality of blocks (B1 to B16). Each block is divided into a plurality of sub blocks each having a plurality of columns. At the time of a cache hit, block address signals (B0, B1) and a column address signal (CA) are simultaneously applied. Any of the plurality of blocks (B1 to B16) is selected in response to the block address signals (B0, B1). At the same time, any of the plurality of registers (16a) corresponding to the selected block is selected in response to the column address signal (CA). The data stored in the register (16a) is thereby read out at a high speed

Abstract translation: 具有内置高速缓冲存储器的半导体存储器件包括存储单元阵列（1）。 存储单元阵列（1）被分成多个块（B1〜B16）。 每个块被分成多个子块，每个子块具有多个列。 在缓存命中时，同时施加块地址信号（B0，B1）和列地址信号（CA）。 响应于块地址信号（B0，B1）选择多个块（B1至B16）中的任一个。 同时，响应于列地址信号（CA）选择对应于所选块的多个寄存器（16a）中的任何一个。 因此，存储在寄存器（16a）中的数据被高速读出

公开(公告)号：US5222047A

公开(公告)日：1993-06-22

申请号：US566809

申请日：1990-08-13

Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Hideto Hidaka

IPC: G11C7/10 ,  G11C8/14 ,  G11C8/18

CPC classification number: G11C8/14 ,  G11C7/1036 ,  G11C7/1039 ,  G11C8/18 ,  H01L2924/01074

Abstract: In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifier are made different for each subblock in the block in which the selected word line is included, whereby the peak current associated with the bit line charge/discharge at the time of activating the sense amplifiers is reduced.

Abstract translation: 在其中存储单元阵列被划分成多个块并且通过块单元执行数据输入/输出的块存取存储器中，每个块被划分成多个子块，并且激活字线和 激活读出放大器的定时对于其中包括所选择的字线的块中的每个子块而言是不同的，从而降低与激活读出放大器时的位线充电/放电相关联的峰值电流。

公开(公告)号：US5179687A

公开(公告)日：1993-01-12

申请号：US542682

申请日：1990-06-25

Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Yoshio Matsuda ,  Mikio Asakura

IPC: G06F12/08 ,  G11C11/4096

CPC classification number: G06F12/0893 ,  G11C11/4096

Abstract: A DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, a plurality of data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive to a row address strobe signal for selecting access to either the data registers or the memory cell array. Upon cache hit, the row address strobe signal is inactivated to cause the selector to select the access to the data registers. Upon cache miss, the row address strobe signal is activated to cause the selector to select the access to the memory cell array.

Abstract translation: 用于简单高速缓冲存储器系统的DRAM包括被划分成多个块的存储单元阵列，与阵列的各个块对应地提供的多个数据寄存器，用于锁存相应块的存储单元数据，以及响应于选择器 用于选择对数据寄存器或存储单元阵列的访问的行地址选通信号。 缓存命中后，行地址选通信号被取消激活，使选择器选择对数据寄存器的访问。 在缓存未命中时，行地址选通信号被激活以使选择器选择对存储单元阵列的访问。

公开(公告)号：US5111386A

公开(公告)日：1992-05-05

申请号：US538605

申请日：1990-06-14

Applicant: Kazuyasu Fujishima ,  Charles A. Hart

Inventor： Kazuyasu Fujishima ,  Charles A. Hart

IPC: G06F12/08 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41

CPC classification number: G11C8/12 ,  G06F12/0893

Abstract: A dynamic random access memory with a fast serial access mode for use in a simple cache system includes a plurality of memory cell blocks prepared by division of a memory cell array, a plurality of data latches each provided for each column in the memory cell blocks and a block selector. When a cache miss signal is produced by the cache system, data on the column in the cell block selected by the block decoder are transferred into the data latches provided for the columns in the selected block after selection. When a cache hit signal is produced by the cache system, the data latches are isolated from the memory cell array. Accessing is made to at least one of the data latches based on an externally applied column address on cache hit, and to at least one of the columns in the selected block based on the column address on cache miss.

Abstract translation: 具有用于简单高速缓存系统的快速串行访问模式的动态随机存取存储器包括通过对存储单元阵列进行划分而分别制备的多个存储单元块，为存储单元块中的每列提供的多个数据锁存器，以及 块选择器。 当由高速缓存系统产生高速缓存未命中信号时，由块解码器选择的单元块中的列上的数据被传送到在选择之后为选定块中的列提供的数据锁存器中。 当缓存命中信号由高速缓存系统产生时，数据锁存器与存储单元阵列隔离。 基于高速缓存命中的外部应用列地址，以及基于高速缓存未命中的列地址的所选块中的至少一个列，对至少一个数据锁存器进行访问。

公开(公告)号：US4896297A

公开(公告)日：1990-01-23

申请号：US112034

申请日：1987-10-23

Applicant: Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

Inventor： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC: G11C8/08

CPC classification number: G11C8/08

Abstract: A circuit for generating a boosted signal for a word line, coupled to a word line driving signal line for transmitting a voltage signal to the word line, coupled to a first power supply, and coupled to a second power supply for providing a voltage higher than the voltage of the first power supply, can supply a compensating voltage for the word line from the second power supply through the word line driving signal line when a voltage of the word line is decreased.

Abstract translation: 一种用于产生用于字线的升压信号的电路，耦合到字线驱动信号线，用于将电压信号传输到字线，耦合到第一电源，并耦合到第二电源，以提供高于 当字线的电压减小时，第一电源的电压可以通过字线驱动信号线从第二电源提供用于字线的补偿电压。

公开(公告)号：US4835743A

公开(公告)日：1989-05-30

申请号：US92615

申请日：1987-09-03

Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Kazutoshi Hirayama

Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Kazutoshi Hirayama

IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409

CPC classification number: G11C7/1033

Abstract: In a semiconductor memory device capable of nibble mode operation, the time period required from the time when CAS signal falls to the time when a data output buffer activating signal rises is made different at the time of a normal mode and at the time of a nibble mode, so that the time period required for reading out data in the nibble mode is reduced as compared with a conventional device.

Abstract translation: 在能够进行半字节模式操作的半导体存储器件中，从正常模式时和在上一时刻起，当＆amp; C＆gt;信号下降到数据输出缓冲器激活信号上升时的时间所需的时间段变得不同 半字节模式，因此与常规设备相比，读取半字节模式中的数据所需的时间段被减少。

公开(公告)号：US4760559A

公开(公告)日：1988-07-26

申请号：US883311

申请日：1986-07-08

Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka

Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka

IPC: G11C11/407 ,  G11C11/408 ,  G11C7/00

CPC classification number: G11C11/4085

Abstract: A dynamic type MOS-RAM constructed of folded type bit lines and having sense operation cycles for amplifying potential difference appearing on respective pairs of bit lines after selection of a word line and restore operation cycles for further amplifying the potential difference on the pairs of bit lines after the sense operation cycles, wherein non-selected word lines are completely brought into electrically floating states in intervals including the sense operation cycles and the restore operation cycles.

Abstract translation: 由折叠型位线构成的具有读出操作周期的动态型MOS-RAM，用于放大在选择字线之后出现在各对位线上的电位差，并且还原操作周期用于进一步放大位线对上的电位差 在感测操作周期之后，其中未选择的字线在包括感测操作周期和恢复操作周期的间隔中完全进入电浮动状态。

公开(公告)号：US4760556A

公开(公告)日：1988-07-26

申请号：US911431

申请日：1986-09-25

Applicant: Mikio Deguchi ,  Kazuyasu Fujishima ,  Yasushi Terada

Inventor： Mikio Deguchi ,  Kazuyasu Fujishima ,  Yasushi Terada

IPC: G11C17/00 ,  G11C11/404 ,  G11C14/00 ,  G11C16/04 ,  G11C11/40

CPC classification number: G11C14/00

Abstract: Each of the memory cells forming a nonvolatile RAM comprises one floating-gate transistor and one capacitor. When the power source is turned on, storage of information is performed according to the amount of electric charge stored in each capacitor. When the power source is turned off, nonvolatile storage of information is performed according to the level of the threshold voltage of each floating-gate transistor.

Abstract translation: 形成非易失性RAM的每个存储单元包括一个浮栅晶体管和一个电容器。 当电源接通时，根据每个电容器中存储的电荷量进行信息存储。 当电源关闭时，根据每个浮栅晶体管的阈值电压的电平执行信息的非易失性存储。

公开(公告)号：US4692901A

公开(公告)日：1987-09-08

申请号：US762632

申请日：1985-08-05

Applicant: Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasumasa Nishimura

Inventor： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasumasa Nishimura

IPC: G11C29/34 ,  G11C7/00

CPC classification number: G11C29/34

Abstract: A semiconductor memory comprises memory cells (15-18, 27-30), a data writing terminal (1), a data readout terminal (48), transistors (3-10, 35-42), address signal input terminals (23-26), subdecode signal input terminals (43-46), driving signal generating circuits (49-52), parallel readout circuits (79-82) and test mode switching signal input terminal (53, 88). In writing of function test data for the memory cells, the driving signal generating circuits turn all of the transistors (3-10) on in response to a test mode switching signal with no regard to address signals, thereby to simultaneously write data in the memory cells (15-18). Further, in readout of the function test data for the memory cells, the parallel readout circuits read the storage contents of the memory cells (27-30) storing the test data in response to a test mode switching signal with no regard to subdecode signals. Logic circuit means (90, 91, 94) may be provided to output logical value corresponding to the test data stored in the memory cells when all of the logical values of the test data are at the same level.

Abstract translation: 半导体存储器包括存储单元（15-18,27-30），数据写入端（1），数据读出端（48），晶体管（3-10,35-42），地址信号输入端（23- 26），子代码信号输入端子（43-46），驱动信号发生电路（49-52），并行读出电路（79-82）和测试模式切换信号输入端子（53,88）。 在写入存储单元的功能测试数据时，驱动信号发生电路响应于测试模式切换信号而使所有晶体管（3-10）响应于地址信号，从而同时将数据写入存储器 细胞（15-18）。 此外，在读出存储单元的功能测试数据时，并行读出电路响应于不考虑子代码信号的测试模式切换信号读取存储测试数据的存储单元（27-30）的存储内容。 可以提供逻辑电路装置（90,91,94）以当测试数据的所有逻辑值处于相同电平时输出与存储在存储单元中的测试数据相对应的逻辑值。