公开(公告)号：US20230317158A1

公开(公告)日：2023-10-05

申请号：US17708541

申请日：2022-03-30

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari

IPC分类号： G11C13/00 ,  H03M13/11

CPC分类号： G11C13/0069 ,  G11C13/004 ,  G11C13/0059 ,  H03M13/1105

摘要： Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

公开(公告)号：US20210280246A1

公开(公告)日：2021-09-09

申请号：US17214162

申请日：2021-03-26

申请人： CROSSBAR, INC.

发明人： Sung Hyun JO

IPC分类号： G11C13/00 ,  H01L27/24 ,  H01L45/00 ,  G11C11/56 ,  G11C11/16

摘要： Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

公开(公告)号：US11068620B2

公开(公告)日：2021-07-20

申请号：US13673951

申请日：2012-11-09

申请人： Crossbar, Inc.

发明人： George Minassian

IPC分类号： G06F21/74

摘要： An example secure circuit device includes a logic layer with a logic circuit, first and second memory layers, and connectors between the logic layer and the memory layers. The logic circuit executes logic operations in response to being in an unlocked state and does not execute logic operations in response to being in a locked state. The logic circuit is in the unlocked state in response to a security key being accessible and in the locked state when the security key is inaccessible. The first memory layer is disposed over a second memory layer with the first and second memory layers being disposed over the logic layer in a monolithic structure. The security key includes a first security key portion disposed in the first memory layer and a second security key portion disposed in the second memory layer.

公开(公告)号：US10796751B1

公开(公告)日：2020-10-06

申请号：US16261696

申请日：2019-01-30

申请人： Crossbar, Inc.

发明人： Sang Nguyen ,  Hagop Nazarian ,  Tianhong Yan

IPC分类号： G11C11/419 ,  G11C8/18 ,  G11C7/10 ,  G11C11/418 ,  G11C7/06 ,  G11C13/00

摘要： A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state, e.g., to a defined higher resistance state or a defined lower resistance state. Other, techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that cause the state change and can do so by comparing the magnitudes or values of two particular current parameters.

公开(公告)号：US10749110B1

公开(公告)日：2020-08-18

申请号：US15486529

申请日：2017-04-13

申请人： Crossbar, Inc.

发明人： Sundar Narayanan ,  Zhen Gu ,  Natividad Vasquez

IPC分类号： H01L45/00

摘要： Two-terminal memory devices can be formed in dielectric material that is electrically insulating and operates as a blocking layer to mitigate diffusion of material from a metal layer. A stack of layers of the two-terminal memory device can be covered with a liner layer that can comprise the dielectric material. Thus, in some implementations, the liner layer and the blocking layer can have a similar etch rate.

公开(公告)号：US10693062B2

公开(公告)日：2020-06-23

申请号：US15370561

申请日：2016-12-06

申请人： Crossbar, Inc.

发明人： Sundar Narayanan ,  Sung Hyun Jo ,  Liang Zhao

IPC分类号： H01L45/00 ,  H01L27/24

摘要： Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can be grown on the silicon bearing layer, and the growth of the interface layer can be regulated with N2O plasma.

公开(公告)号：US20190259452A1

公开(公告)日：2019-08-22

申请号：US16398943

申请日：2019-04-30

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari ,  Hagop Nazarian

IPC分类号： G11C13/00 ,  G11C11/16 ,  G11C15/04 ,  G06F12/02 ,  G11C15/02

摘要： A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.

公开(公告)号：US10199105B2

公开(公告)日：2019-02-05

申请号：US15592999

申请日：2017-05-11

申请人： Crossbar, Inc.

发明人： Lin Shih Liu ,  Hagop Nazarian

IPC分类号： G11C5/06 ,  G11C14/00 ,  G11C11/419 ,  G11C13/00 ,  G11C11/412

摘要： Providing for a configuration cells for junction nodes of a field programmable gate array (FPGA) is described herein. By way of example, a configuration cell can comprise non-volatile resistive switching memory to facilitate programmable storage of data as an input to a control circuit of a junction node. The control circuit can activate or deactivate a junction node of the FPGA in response to a value of the data stored in the non-volatile resistive switching memory. The control circuit can comprise an SRAM circuit for fast operation of the junction node. Moreover, the non-volatile memory of the configuration cell facilitates fast power-up of the control circuit utilizing data stored in the resistive switching memory, and minimizes power consumption associated with storing the data.

公开(公告)号：US10079060B2

公开(公告)日：2018-09-18

申请号：US15495574

申请日：2017-04-24

申请人： Crossbar, Inc.

发明人： Sung Hyun Jo ,  Hagop Nazarian ,  Lin Shih Liu

IPC分类号： G11C13/00 ,  G11C14/00

CPC分类号： G11C13/004 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0061 ,  G11C14/00 ,  G11C14/0045 ,  G11C29/026 ,  G11C29/028 ,  G11C2013/0071 ,  G11C2213/51 ,  G11C2213/73 ,  G11C2213/76

摘要： Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

公开(公告)号：US10050629B1

公开(公告)日：2018-08-14

申请号：US15610829

申请日：2017-06-01

申请人： Crossbar, Inc.

发明人： Mehdi Asnaashari ,  Hagop Nazarian

IPC分类号： H03K19/17 ,  G11C19/38 ,  H03K19/177 ,  H03K19/00

摘要： A method for an FPGA includes programming a RRAM memory array with a first bit pattern, shifting the first bit pattern to a shift register array, employing the first bit pattern in operation of the FPGA, programming a RRAM memory array with a second bit pattern concurrent the employing the bit pattern in operation of the FPGA, shifting the second bit pattern to the shift register array, and employing the second bit pattern in operation of the FPGA.