公开(公告)号：US06867080B1

公开(公告)日：2005-03-15

申请号：US10460165

申请日：2003-06-13

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC: H01L21/20 ,  H01L21/268 ,  H01L21/28 ,  H01L21/321 ,  H01L21/8234 ,  H01L21/338 ,  H01L21/331 ,  H01L21/94

CPC classification number: H01L21/28176 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/321 ,  H01L21/823437 ,  Y10S438/926

Abstract: A method is provided for eliminating uneven heating of substrate active areas during laser thermal annealing (LTA) due to variations in gate electrode density. Embodiments include adding dummy structures, formed simultaneously with the gate electrodes, to “fill in” the spaces between isolated gate electrodes, such that the spacing between the gate electrodes and the dummy structures is the same as the spacing between the densest array of device structures on the substrate surface. Since the surface features (i.e., the gate electrodes and the dummy structures) appear substantially uniform to the LTA laser, the laser radiation is uniformly absorbed by the substrate, and the substrate surface is evenly heated.

Abstract translation: 提供了一种用于消除激光热退火（LTA）期间基板有源区的不均匀加热的方法，这是由于栅电极密度的变化。 实施例包括添加与栅电极同时形成的虚拟结构以“填充”隔离栅电极之间的空间，使得栅电极和虚拟结构之间的间隔与器件结构最密集阵列之间的间隔相同 在基板表面上。 由于表面特征（即，栅电极和虚拟结构）对于LTA激光器而言基本上均匀，激光辐射被基板均匀地吸收，并且基板表面被均匀地加热。

公开(公告)号：US20050006666A1

公开(公告)日：2005-01-13

申请号：US10913409

申请日：2004-08-09

Applicant: Bin Yu ,  Shibly Ahmed ,  Judy An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

Inventor： Bin Yu ,  Shibly Ahmed ,  Judy An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L31/072

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method of forming a semiconductor device includes forming a fin on an insulating layer, where the fin includes a number of side surfaces, a top surface and a bottom surface. The method also includes forming a gate on the insulating layer, where the gate has a substantially U-shaped cross-section at a channel region of the semiconductor device.

Abstract translation: 形成半导体器件的方法包括在绝缘层上形成翅片，其中鳍片包括多个侧表面，顶表面和底表面。 该方法还包括在绝缘层上形成栅极，其中栅极在半导体器件的沟道区域具有基本上U形的横截面。

公开(公告)号：US06827840B2

公开(公告)日：2004-12-07

申请号：US10170903

申请日：2002-06-13

Applicant: Kalle Levon ,  Bin Yu ,  Yanxiu Zhou

Inventor： Kalle Levon ,  Bin Yu ,  Yanxiu Zhou

IPC: G01N27327

CPC classification number: G01N27/3335

Abstract: Enantiomeric resolution is realized by combining an electrochemical method with ligand exchange (LE) in a novel electrochemical method named chiral ligand exchange potentiometry. Chiral selector ligands preferentially recognize certain enantiomers and undergo ligand exchange with the enantiomeric labile coordination complexes to form diastereoisomeric complexes. These complexes can form in solution and be recognized by an unmodified electrode, or they can be immobilized on the surface of a modified electrode (chiral sensor) incorporated with the chiral selector ligand by polysiloxane monolayer immobilization (PMI). Considerable stereoselectivity occurs in the formation of these diastereoisomeric complexes, and their net charges (Nernst factors) are different, thus enabling enantiomers to be distinguished by potentiometric electrodes without any pre-separation processes.

Abstract translation: 通过将电化学方法与配体交换（LE）结合在一种称为手性配体交换电位法的新型电化学方法中来实现对映体拆分。 手性选择配体优先识别某些对映异构体并与对映异构体不稳定配位络合物进行配体交换以形成非对映异构体复合物。 这些配合物可以在溶液中形成并被未改性的电极识别，或者它们可以通过聚硅氧烷单层固定化（PMI）固定在掺入手性选择配体的改性电极（手性传感器）的表面上。 在形成这些非对映异构体复合物时会产生相当大的立体选择性，它们的净电荷（能斯特因子）是不同的，因此能够通过电位电极区分对映异构体，而无需任何预分离过程。

公开(公告)号：US06825115B1

公开(公告)日：2004-11-30

申请号：US10341436

申请日：2003-01-14

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L2144

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665

Abstract: Dopant deactivation, particularly at the Si/silicide interface, is avoided by forming deep source/drain implants after forming silicide layers on the substrate and activating the source/drain regions by laser thermal annealing. Embodiments include forming source/drain extensions, forming metal silicide layers on the substrate surface and gate electrode, forming preamorphized regions under the metal silicide layers in the substrate, ion implanting to form deep source/drain implants overlapping the preamorphized regions and extending deeper into the substrate then the preamorphized regions, and laser thermal annealing to activate the deep source/drain regions.

Abstract translation: 通过在衬底上形成硅化物层并通过激光热退火来激活源极/漏极区域之后形成深源极/漏极注入来避免掺杂失活，特别是Si /硅化物界面。 实施例包括形成源极/漏极延伸部，在衬底表面上形成金属硅化物层和栅电极，在衬底中的金属硅化物层下方形成预变形区域;离子注入，以形成与预变形区域重叠的深源/漏植入物， 衬底然后是前变形区域，激光热退火激活深源/漏区。

公开(公告)号：US06815268B1

公开(公告)日：2004-11-09

申请号：US10301732

申请日：2002-11-22

Applicant: Bin Yu ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy

Inventor： Bin Yu ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method of forming a gate in a FinFET device includes forming a fin on an insulating layer, forming source/drain regions and forming a gate oxide on the fin. The method also includes depositing a gate material over the insulating layer and the fin, depositing a barrier layer over the gate material and depositing a bottom anti-reflective coating (BARC) layer over the barrier layer. The method further includes forming a gate mask over the BARC layer, etching the BARC layer, where the etching terminates on the barrier layer, and etching the gate material to form the gate.

Abstract translation: 在FinFET器件中形成栅极的方法包括在绝缘层上形成鳍片，形成源极/漏极区域并在鳍片上形成栅极氧化物。 该方法还包括在绝缘层和鳍上沉积栅极材料，在栅极材料上沉积阻挡层并在阻挡层上沉积底部抗反射涂层（BARC）层。 该方法还包括在BARC层上形成栅极掩模，蚀刻BARC层，其中蚀刻在阻挡层上终止，并蚀刻栅极材料以形成栅极。

公开(公告)号：USRE38608E1

公开(公告)日：2004-10-05

申请号：US10052843

申请日：2002-01-17

Applicant: Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

Inventor： Bin Yu ,  Chenming Hu ,  Ya-Chin King ,  Jeffrey T. Pohlman ,  Rita Trivedi

IPC: H01L2900

CPC classification number: H01L29/8618 ,  H01L29/866

Abstract: A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p− region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region. The peak dopant concentration of the n+ layers should be about 1.5E18 cm−3, the peak dopant concentration of the p+ layer should be between about 1 to about 5 times the peak concentration of the n+ layer, and the dopant concentration of the p− layer should be between about 0.5E14 cm−3 and about 1.OE17 cm−3. The junction depth of the fourth (n+) region should be greater than about 0.3 &mgr;m. The thickness of the third (p+) region should be between about 0.3 &mgr;m and about 2.0 &mgr;m, and the thickness of the second (p−) region should be between about 0.5 &mgr;m and about 5.0 &mgr;m.

公开(公告)号：US06787852B1

公开(公告)日：2004-09-07

申请号：US10278420

申请日：2002-10-23

Applicant: Bin Yu ,  Ralf van Bentum

Inventor： Bin Yu ,  Ralf van Bentum

IPC: H01L2701

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer. The active layer has an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween. The source and the drain have a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon. The silicon-geranium regions form heterojunction portions respectively along the source/body junction and the drain/body junction.

Abstract translation: 绝缘体上半导体（SOI）器件。 SOI器件包括其上设置有掩埋氧化物层的衬底和设置在掩埋氧化物层上的有源层。 有源层具有由隔离区域限定的有源区域，有源区域具有源极和漏极，其间设置有主体。 源极和漏极具有选择性地生长的硅 - 锗区域，其设置在选择性生长的硅的上层下方。 硅锗天线分别沿着源极/主体结和漏极/主体结形成异质结部分。

公开(公告)号：US06784101B1

公开(公告)日：2004-08-31

申请号：US10146029

申请日：2002-05-16

Applicant: Bin Yu ,  David Wu

Inventor： Bin Yu ,  David Wu

IPC: H01L2144

CPC classification number: H01L21/022 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/28194 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/1054 ,  H01L29/517

Abstract: A semiconductor device is formed by providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice therein, forming a thin buffer/interfacial layer of a low-k dielectric material on the upper surface of the semiconductor substrate, and forming a layer of a high-k dielectric material on the thin buffer/interfacial layer of a low-k dielectric material. Embodiments include forming the thin buffer/interfacial layer and high-k layer at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of the strained lattice semiconductor layer.

Abstract translation: 半导体器件通过在其上表面设置包含应变晶格半导体层并在其中具有预选量的晶格的半导体衬底形成，在上表面上形成低k介电材料的薄缓冲/界面层 并且在低k电介质材料的薄缓冲层/界面层上形成高k电介质材料层。 实施例包括在足以实现相应电介质层的形成的最小温度下形成薄缓冲层/界面层和高k层，而不会引起应变晶格半导体层的应变弛豫或至少最小化应变弛豫。

公开(公告)号：US06774436B1

公开(公告)日：2004-08-10

申请号：US09900400

申请日：2001-07-05

Applicant: Bin Yu ,  Ralf van Bentum

Inventor： Bin Yu ,  Ralf van Bentum

IPC: H01L310392

CPC classification number: H01L29/66772 ,  H01L29/78612 ,  H01L29/78624

Abstract: A semiconductor-on-insulator (SOI) device. The SOi device includes a substrate, an insulator layer disposed on the substrate and an active region disposed on the insulator layer. The active region includes a source, a drain, and a body disposed therebetween. The source and body form an abrupt or hyperabrupt source/body junction. A gate is disposed on the body to operatively form a transistor. An implanted region forms an interface between the body and the drain, the implanted region formed by tilted atom implantation in a direction towards the active region and under the gate from an angle tilted towards the drain with respect to vertical, the implanted region resulting in the formation of a graded drain/body junction. Also disclosed is a method of fabricating the SOI device.

Abstract translation: 绝缘体上半导体（SOI）器件。 SOi器件包括衬底，设置在衬底上的绝缘体层和设置在绝缘体层上的有源区。 有源区域包括源极，漏极和设置在它们之间的主体。 来源和身体形成突然或超破坏的源/体结。 栅极设置在主体上以可操作地形成晶体管。 植入区域在主体和漏极之间形成界面，通过倾斜的原子注入在朝向有源区域的方向上形成的注入区域和从栅极相对于垂直方向朝向漏极倾斜的角度形成注入区域， 形成分级排水/身体结。 还公开了一种制造SOI器件的方法。

公开(公告)号：US06746944B1

公开(公告)日：2004-06-08

申请号：US10341345

申请日：2003-01-14

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L213205

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/7833

Abstract: Semiconductor devices with reduced NiSi/Si interface contact resistance are fabricated by forming preamorphized regions in a substrate at a depth overlapping the subsequently formed NiSi/Si interface, ion implanting impurities to form deep source/drain implants overlapping the preamorphized regions deeper in the substrate and laser thermal annealing to activate the deep source/drain regions. Nickel silicide layers are then formed in a main surface of the substrate and on the gate electrode. Embodiments include forming deep source/drain regions with an activated impurity concentration of 1×1020 to 1×1021 atoms/cm3 at the NiSi/Si interface.

Abstract translation: 具有降低的NiSi / Si界面接触电阻的半导体器件通过在与随后形成的NiSi / Si界面重叠的深度的衬底中形成预变形区域，离子注入杂质以形成与衬底中较深的预变形区域重叠的深源/漏注入; 激光热退火激活深源/漏区。 然后在衬底的主表面和栅电极上形成硅化镍层。 实施例包括在NiSi / Si界面处形成具有1×10 20至1×10 21原子/ cm 3的活化杂质浓度的深源/漏区。