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公开(公告)号：US07690024B2
公开(公告)日：2010-03-30
申请号：US11350075
申请日：2006-02-09
CPC分类号： H04L63/0853 , H04L63/1441 , H04W12/06 , H04W12/12
摘要： It is made possible to prevent “spoofing” and incur no additional management cost as effectively as possible. An authenticated device includes: at least one authenticated element that generates an output signal with characteristics spontaneously varying, at the time of manufacturing, with respect to a continuous input signal. The characteristics of the authenticated element are used as information unique to an individual.
摘要翻译： 有可能防止“欺骗”，并且不会有效地增加管理成本。 认证设备包括：至少一个认证元件，其在制造时产生具有相对于连续输入信号自发变化的特性的输出信号。 被认证的元素的特征被用作个体唯一的信息。
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62.发明授权公开(公告)号：US07569879B2
公开(公告)日：2009-08-04
申请号：US11699334
申请日：2007-01-30
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11556 , H01L27/11568
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, plural semiconductor columns arranged in a matrix form on the substrate, plural first conductive areas zonally formed in a column direction on the substrate between the semiconductor columns and functioning as word lines, plural second conductive areas formed at tops of the semiconductor columns, respectively, plural bit lines connecting the second conductive areas in a row direction, plural channel areas respectively formed in the semiconductor columns between the first and second conductive areas and contacting the first and second conductive areas, plural third conductive areas continuously formed via first insulating films above the substrate and opposite to the channel areas in the column direction between the semiconductor columns and functioning as control gates, and plural charge accumulation areas respectively formed via second insulating films at upper portions of the channel areas at a position higher than the third conductive areas.
摘要翻译： 非易失性半导体存储器件包括：半导体衬底，以矩阵形式布置在衬底上的多个半导体柱，在半导体柱之间的衬底上的列方向上分区形成的多个第一导电区域，并且用作字线，形成多个第二导电区域 在半导体柱的顶部分别分别连接在行方向上的第二导电区域的多个位线，分别形成在第一和第二导电区域之间的半导体柱中并与第一和第二导电区域接触的多个沟道区域，多个第三导电 通过基板上方的第一绝缘膜连续形成的区域，并且与半导体柱之间的列方向上的沟道区域相对，并且用作控制栅极，以及分别在沟道区域的上部经由第二绝缘膜形成的多个电荷累积区域 位置高 她比第三个导电区域。
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公开(公告)号：US20090186474A1
公开(公告)日：2009-07-23
申请号：US12318493
申请日：2008-12-30
IPC分类号： H01L21/302
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film.
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公开(公告)号：US20090083202A1
公开(公告)日：2009-03-26
申请号：US12211739
申请日：2008-09-16
申请人： CHIKA TANAKA , Atsuhiro Kinoshita
发明人： CHIKA TANAKA , Atsuhiro Kinoshita
CPC分类号： G06N3/063 , G11C16/22 , G11C27/005
摘要： A semiconductor storage device includes a storage part including a plurality of nonvolatile semiconductor memory cells each having a conductive path, a charge storage layer and a control gate electrode. The device further includes a plurality of first input terminals each connected to one end of the conductive path of each nonvolatile semiconductor memory cell, a plurality of second input terminals each connected to the control gate of each nonvolatile semiconductor memory cell, and an output end connected to the other ends of the conductive paths of the plurality of nonvolatile semiconductor memory cells, respectively.
摘要翻译： 一种半导体存储装置，包括具有导电路径的多个非易失性半导体存储单元，电荷存储层和控制栅电极的存储部。 该装置还包括多个第一输入端子，每个第一输入端子连接到每个非易失性半导体存储单元的导电路径的一端，多个第二输入端子，每个第二输入端子连接到每个非易失性半导体存储器单元的控制栅极，并且输出端连接 分别连接到多个非易失性半导体存储单元的导电路径的另一端。
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公开(公告)号：US20080179752A1
公开(公告)日：2008-07-31
申请号：US11898295
申请日：2007-09-11
IPC分类号： H01L29/78 , H01L21/336 , H01L23/48
CPC分类号： H01L29/66795 , H01L21/26513 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/47 , H01L29/66507 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66643 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.
摘要翻译： 公开了具有应变通道区域的金属绝缘体半导体场效应晶体管（MISFET）。 还公开了一种制造具有低电阻结界面的半导体器件的方法。 该制造方法包括在硅衬底上形成栅电极的步骤，其间夹有栅绝缘膜。 然后，在栅极两侧的衬底表面中或其上形成一对重掺杂的p（p + SUP +）型扩散层，使其浓度达到5×10 19 原子/ cm 3以上且小于或等于1×10 21原子/ cm 3。 接下来，在各层施加压缩应变的状态下，通过与金属反应来硅化p + + +层。
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66.发明申请公开(公告)号：US20080111178A1
公开(公告)日：2008-05-15
申请号：US11835694
申请日：2007-08-08
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。
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公开(公告)号：US20070247906A1
公开(公告)日：2007-10-25
申请号：US11723335
申请日：2007-03-19
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11519 , H01L29/785
摘要： A Fin-type memory cell according to an example of the present invention includes a fin-shaped active area, a floating gate along a side surface of the fin-shaped active area, and two control gate electrodes arranged in a longitudinal direction of the fin-shaped active area, and sandwiching the floating gate.
摘要翻译： 根据本发明的实施例的鳍型存储单元包括鳍状有源区域，沿着鳍状有源区域的侧表面的浮置栅极和沿翅片的纵向布置的两个控制栅极电极 形状的活动区域，并夹着浮动门。
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公开(公告)号：US20070052031A1
公开(公告)日：2007-03-08
申请号：US11404075
申请日：2006-04-14
申请人： Atsuhiro Kinoshita
发明人： Atsuhiro Kinoshita
IPC分类号： H01L23/62
CPC分类号： H01L27/0251 , H01L29/665 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： It is made possible to easily set a protection voltage even when a semiconductor device to be protected includes a gate insulating film having a low dielectric breakdown voltage. A semiconductor device includes: a MOS transistor including a first gate insulating film provided on a first element region of first conductivity-type in a semiconductor, a first gate electrode provided on the first gate insulating film, and first impurity regions of second conductivity-type provided in the first element region on both sides of the first gate electrode; and an ESD protection element including a second gate insulating film provided on a second element region of first conductivity-type in the semiconductor substrate and having substantially the same thickness as the first gate insulating film, a second gate electrode provided on the second gate insulating film and connected to the first gate electrode, and second impurity regions of second conductivity-type provided in the second element region on both sides of the second gate electrode.
摘要翻译： 即使要被保护的半导体器件包括具有低介电击穿电压的栅极绝缘膜，也可以容易地设定保护电压。 半导体器件包括：MOS晶体管，包括设置在半导体中的第一导电类型的第一元件区域上的第一栅极绝缘膜，设置在第一栅极绝缘膜上的第一栅极电极和第二导电类型的第一杂质区域 设置在所述第一栅电极的两侧的所述第一元件区域中; 以及ESD保护元件，包括设置在半导体衬底中的第一导电类型的第二元件区上并具有与第一栅极绝缘膜基本相同的厚度的第二栅极绝缘膜，设置在第二栅极绝缘膜上的第二栅电极 并且连接到第一栅电极，以及设置在第二栅电极两侧的第二元件区中的第二导电类型的第二杂质区。
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公开(公告)号：US20060220131A1
公开(公告)日：2006-10-05
申请号：US11384269
申请日：2006-03-21
IPC分类号： H01L21/8234 , H01L27/12 , H01L21/336 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823437 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/78618
摘要： It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions. There are provided: a first semiconductor layer of a first conductivity type in a substantially a rectangular solid shape formed on a substrate; a gate electrode formed on a pair of first side portions of the first semiconductor layer facing to each other with a gate insulating film being placed between the gate electrode and the first side portions; a second semiconductor layer of the first conductivity type connected to bottom portions of a pair of second side portions of the first semiconductor layer placed in a substantially perpendicular direction with respect to the first side portions, the second semiconductor layer extending along the substantially perpendicular direction; a first impurity region of a second conductivity type formed in the second semiconductor layer; second impurity regions formed on the pair of side portions of the first semiconductor layer and connected to the first impurity region; and a channel region formed between the second impurity regions of the first semiconductor layer.
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70.发明授权公开(公告)号：US08710573B2
公开(公告)日：2014-04-29
申请号：US12831323
申请日：2010-07-07
IPC分类号： H01L29/788
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.
摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。
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