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    WLAN receiver early power down based on center frequency offset detection
    55.
    发明授权
    WLAN receiver early power down based on center frequency offset detection 有权

    公开(公告)号：US11627531B2

    公开(公告)日：2023-04-11

    申请号：US17106109

    申请日：2020-11-29

    Applicant: Silicon Laboratories, Inc.

    Inventor： Sriram Mudulodu

    IPC: H04W52/02 ,  H04L27/26

    Abstract: A wireless local area network (WLAN) station receiver has a center frequency offset (CFO) estimator and an CFO table with an association between a CFO value from a recently received access point packet for which the station is associated according to 802.11. The receiver performs a comparison between the CFO estimate of the received packet and the CFO value from the CFO database, and powers the receiver down if the comparison exceeds a threshold. The threshold may be an absolute value in parts per million, or may include a time drift compensation component.

    DUAL-BAND OPERATION OF A RADIO DEVICE
    56.
    发明申请
    DUAL-BAND OPERATION OF A RADIO DEVICE 有权

    公开(公告)号：US20230099832A1

    公开(公告)日：2023-03-30

    申请号：US17490255

    申请日：2021-09-30

    Applicant: Silicon Laboratories Inc.

    Inventor： Euisoo Yoo ,  Arup Mukherji ,  Rangakrishnan Srinivasan ,  Vitor Pereira ,  Zhongda Wang ,  Sriharsha Vasadi

    IPC: H04B1/00 ,  H03F3/195 ,  H03H7/38

    Abstract: In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.

    System and method of performing discrete frequency transform for receivers using single-bit analog to digital converters
    57.
    发明授权
    System and method of performing discrete frequency transform for receivers using single-bit analog to digital converters 有权

    公开(公告)号：US11601133B2

    公开(公告)日：2023-03-07

    申请号：US17081707

    申请日：2020-10-27

    Applicant: Silicon Laboratories Inc.

    Inventor： Anant Verma

    IPC: H03M1/00 ,  H03M1/10 ,  H03M1/12 ,  G06F7/50 ,  G06F7/49 ,  G06F7/523 ,  G06F7/72

    Abstract: A system and method for performing discrete frequency transform including a pair of single-bit analog to digital converters (ADCs), a phase converter, a memory, a discrete frequency transform converter and summation circuitry. The ADCs convert an analog input signal into N pairs of binary in-phase and quadrature component samples each being one of four values at a corresponding one of four phases. The phase converter determines a phase value for each pair of component samples. The memory stores a set of discrete frequency transform coefficient values based on N. The discrete frequency transform converter uses a phase value and a pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a discrete frequency component for each pair of phase component samples. The summation circuitry sums the corresponding N frequency domain components for determining a frequency domain value for the selected frequency bin.

    System Clock Spur Reduction in OFDM Receiver
    58.
    发明申请
    System Clock Spur Reduction in OFDM Receiver 有权

    公开(公告)号：US20230041647A1

    公开(公告)日：2023-02-09

    申请号：US17395869

    申请日：2021-08-06

    Applicant: Silicon Laboratories Inc.

    Inventor： Sriram MUDULODU

    IPC: H04B1/16 ,  H04L5/00 ,  H04B1/10 ,  G06F1/08 ,  H03L7/07

    Abstract: A receiver for OFDM subcarriers has a first mode and a second mode. In the first mode, a tunable system clock is output at a nominal frequency, and in the second mode, the tunable system clock is offset so that a harmonic of the tunable system clock coincides with a particular OFDM subcarrier. The tunable system clock is coupled to a programmable modem PLL clock generator which generates clocks for an A/D converter coupled to a baseband processor which is also coupled to the programmable modem PLL clock generator. The programmable modem PLL clock generator is programmed to maintain a constant output frequency of each output in the first mode and the second mode.

    Dual-Mode Power Amplifier For Wireless Communication
    59.
    发明申请
    Dual-Mode Power Amplifier For Wireless Communication 有权

    公开(公告)号：US20230006621A1

    公开(公告)日：2023-01-05

    申请号：US17363049

    申请日：2021-06-30

    Applicant: Silicon Laboratories Inc.

    Inventor： Ruifeng Sun ,  Sherry Wu ,  Michael S. Johnson ,  Vitor Pereira

    IPC: H03F3/24 ,  H03F1/02 ,  H04B1/04 ,  H04L27/12

    Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

    Feeding Circuit Layout for 4 x 4 linear AoX arrays
    60.
    发明申请
    Feeding Circuit Layout for 4 x 4 linear AoX arrays 有权

    公开(公告)号：US20220416440A1

    公开(公告)日：2022-12-29

    申请号：US17830548

    申请日：2022-06-02

    Applicant: Silicon Laboratories Inc.

    Inventor： Ádám Süle ,  Attila Zólomy ,  Szabolcs Lõrincz ,  Terry Lee Dickey

    IPC: H01Q21/06 ,  H01Q21/00 ,  H05K1/02 ,  H01Q1/48

    Abstract: A printed circuit board having an AoX antenna array and a feeding circuit is disclosed. The AoX antenna array has patch antenna disposed on a top layer of the printed circuit board, while the feeding circuit is disposed on the bottom layer. The signal traces that connect the ports of the antenna unit cells to the antenna selection switches are routed so that all are roughly equal in length with a minimal length of parallel sections between signal traces. Thus, the signal traces in the feeding circuit are created so as to minimize phase difference between signal traces and to minimize coupling. Coplanar waveguides, which utilize blind vias are used to further reduce coupling.

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