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公开(公告)号：US10593280B2
公开(公告)日：2020-03-17
申请号：US15740458
申请日：2017-10-21
Inventor： Mang Zhao
IPC: G09G3/36
Abstract: The present disclosure provides a scanning driving circuit and a display device. The scanning driving circuit includes a plurality of stages of scanning driving units in cascade connection. The plurality of stages of scanning driving units include a first stage scanning driving unit, a plurality of intermediate stage scanning driving units and a last stage scanning driving unit each including a forward and reverse scanning circuit configured to control the scanning driving circuit to forward scanning or reverse scanning, an input circuit configured to charge a pull-up control signal point, a latch circuit configured to latch a signal of the pull-up control signal point, an output circuit configured to generate a scanning driving signal, and a reset circuit configured to reset the pull-up control signal point, which reduces the number of signal lines, simplifies the signal line design, saves space and facilitates the narrow frame design.
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公开(公告)号：US10115363B2
公开(公告)日：2018-10-30
申请号：US14917947
申请日：2016-02-22
Inventor： Mang Zhao
Abstract: The present disclosure relates to a gate driving circuit and the LCD thereof. The input circuit generates second control signals in accordance with up-level normal-phase scanning driving signals, up-level inverting-phase scanning driving signals, and first control signals outputted by the latch circuit. The reset and control circuit generates third control signals in accordance with reset signals, the first control signals, and the second control signals. The inverting circuit performs an inverting process at least once toward the third control signals, and generates fourth control signals, the output circuit generates current-level normal-phase scanning driving signals and the current-level inverting-phase scanning driving signals in accordance with the fourth control signals and first clock signals, The latch circuit generates the first control signals in accordance with the third control signals and second clock signals, and latches or changes a voltage state of the third control signals in accordance with the second clock signals.
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公开(公告)号：US10089916B2
公开(公告)日：2018-10-02
申请号：US15316155
申请日：2016-11-04
Inventor： Mang Zhao
Abstract: The disclosure discloses a flat panel display device and a scan driving circuit thereof. The scan driving circuit includes a plurality of cascaded scan drivers, each of the scan drivers includes a forward/backward scanning circuit, an output circuit, a pull-down circuit and a pull-down control circuit, the forward/backward scanning circuit is configured to control the scan drivers to scan forward or backward, the output circuit outputs a first scanning signal, a second scanning signal and a third scanning signal. The first scanning signal, the second scanning signal and the third scanning signal are output by sharing the forward/backward scanning circuit, the pull-down circuit and the pull-down control circuit according to the disclosure, which can reduce the amount of thin film transistors of the scan driving circuit and spare space that are further beneficial for narrow frame design.
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公开(公告)号：US09922611B2
公开(公告)日：2018-03-20
申请号：US14915892
申请日：2016-01-28
IPC: G09G3/36 , H01L27/12 , G02F1/1333 , H01L29/786 , G02F1/1362 , G11C19/18
CPC classification number: G09G3/3674 , G02F1/13 , G02F1/1333 , G02F1/1362 , G09G3/36 , G09G2310/0286 , G11C19/184 , G11C19/28 , H01L27/1222 , H01L27/1237 , H01L29/78651
Abstract: The invention provides a GOA circuit for narrow border LCD panel, by disposing a first node leakage prevention unit (700) comprised of ninth TFT (T9), tenth TFT (T10) and third capacitor (C3), wherein the ninth TFT (T9) has gate and source connected to the output clock signal (CK) to form a diode structure to charge the third capacitor (C3) and fourth node (H(n)) to high voltage; the tenth TFT (T10) clears the fourth node during stage-propagated signal duration to ensure normal charging for the first node (Q(n)). The GOA circuit is applicable to dual-side progressive scanning architecture and also to dual-side interlaced scanning architecture, and able to prevent current leakage in the first node under dual-side interlaced scanning architecture to ensure stable operation of circuit and improve reliability of GOA circuit. Moreover, with only two clock signals on each side, the invention is suitable for narrow border display panel.
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公开(公告)号：US20180059829A1
公开(公告)日：2018-03-01
申请号：US14917568
申请日：2016-01-29
Inventor： Caiqin Chen , Mang Zhao
CPC classification number: G09G3/3677 , G02F1/13338 , G02F1/13454 , G06F3/0412 , G06F3/0416 , G09G3/36 , G09G3/3659 , G09G2300/0408 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G09G2310/08 , G11C19/28
Abstract: The present invention provides a GOA circuit applied for the In Cell type touch display panel. The third transmission gate (TG3) comprising the second P-type thin film transistor (T2) and the third N-type thin film transistor (T3), the first P-type thin film transistor (T1) and the fourth N-type thin film transistor (T4) are added in the output buffer module (600), and the touch control signal (TCK) and the inverted touch control signal (XTCK) are introduced to control the working status of the output buffer module (600). Thus, in the touch scan stage, the third transmission gate (TG3) is deactivated, and the first, the fourth thin film transistors (T1, T4) are activated, and the gate scan driving signal output end (Gate(N)) is floating, and similarly jumps between high, low voltage levels along with that the touch scan driving signal jumps between high, low voltage levels.
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Patent Agency Ranking
公开(公告)号：US09899528B2
公开(公告)日：2018-02-20
申请号：US14890698
申请日：2015-10-21
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng Xiao , Mang Zhao
IPC: H01L29/10 , H01L29/786 , H01L29/417 , H01L25/065 , G03F1/22
CPC classification number: H01L29/78621 , G03F1/22 , H01L25/0655 , H01L29/41733 , H01L29/66765 , H01L29/78624 , H01L29/78678 , H01L29/78696
Abstract: The disclosure provides a manufacturing method for TFT array substrate, a TFT array substrate and a display device. The manufacturing method includes following steps: in sequence, forming a gate pattern layer, a gate insulating layer, a patterned poly-silicon layer, a separation layer on s substrate, and adopting a mask to form a source pattern layer and a drain pattern layer on the separation layer by photolithography processes. The source pattern layer and the drain pattern layer are connected to the patterned poly-silicon layer. The mask blocks one side of the channel area, and the same mask is adopted to form a lightly doped area on the other side of the channel area not blocked by the mask. The disclosure may reduce production costs and has great design flexibility.
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公开(公告)号：US09835917B2
公开(公告)日：2017-12-05
申请号：US14773355
申请日：2015-08-11
IPC: G01R31/28 , G02F1/1345 , G02F1/1362 , G02F1/1368 , H01L21/66 , H01L27/12 , H01L29/786 , G09G3/00
CPC classification number: G02F1/136286 , G01R31/2825 , G02F1/13454 , G02F1/1368 , G02F2001/136254 , G02F2202/104 , G09G3/006 , G09G2330/12 , H01L22/34 , H01L27/1222 , H01L27/124 , H01L29/78672
Abstract: A baseplate circuit is disclosed. The baseplate comprises an IC region, a plurality of WOA regions, a plurality of GOA regions, and a plurality of switches. Each WOA region comprises a plurality of baseplate conducting wires, each of the baseplate conducting wires is electrically connected with the IC region. Each GOA region comprises a plurality of gate lines, each of the gate lines is electrically connected with one of the baseplate conducting wires. Each of the switches is used to electrically connect one of the gate lines and one of the baseplate conducting wires.
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公开(公告)号：US09824621B2
公开(公告)日：2017-11-21
申请号：US14778281
申请日：2015-04-03
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng Xiao , Mang Zhao
IPC: G09G3/20 , G09G3/3266 , G09G3/36 , G11C19/28
CPC classification number: G09G3/2085 , G09G3/3266 , G09G3/3674 , G09G3/3677 , G09G2230/00 , G09G2300/0408 , G09G2300/0833 , G09G2310/021 , G09G2310/0243 , G09G2310/0286 , G09G2310/08 , G11C19/28 , G11C19/287
Abstract: A gate drive circuit and a display device are provided. The present disclosure pertains to the technical field of display technology and solves the technical problem of wide frame of the existing display device. The shifting register is configured to output primary drive signal into a first follower and a second follower in consecutive first scanning period t1 and second scanning period t2. The first follower is configured to output gate drive signal to a first gate line in t1 under the driving of the primary drive signal; and the second follower is configured to output the gate drive signal to a second gate line in t2 under the driving of the primary drive signal. The present disclosure can be applied to display devices, such as liquid crystal display devices and OLED display devices, and the like.
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公开(公告)号：US09805675B2
公开(公告)日：2017-10-31
申请号：US15012787
申请日：2016-02-01
IPC: G06F1/00 , G09G3/36 , H03K17/687
CPC classification number: G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2310/08 , H03K17/6871
Abstract: The disclosure discloses a GOA circuit based on the LTPS, including a modulation circuit; a charging circuit; an input signal terminal and an output signal terminal. The modulation circuit and the charging circuit are connected to the input signal terminal and the output signal terminal to make the modulation circuit and the charging circuit in parallel connection, and the charging circuit is used to charge the output scanning signal during the mutation process to increase the mutation speed of the output scanning signal. Wherein the charging circuit is a switch including a control terminal, a first terminal, and a second terminal; the input signal terminal is connected to the first terminal of the charging circuit. The output signal terminal is connected to the second terminal and the control terminal of the charging circuit separately. A display apparatus including the GOA circuit based on the LTPS is also provided.
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公开(公告)号：US09799286B2
公开(公告)日：2017-10-24
申请号：US14781293
申请日：2015-08-28
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Mang Zhao , Juncheng Xiao , Yong Tian
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2300/0809 , G09G2310/08
Abstract: A GOA circuit and LCD are disclosed. The GOA circuit includes cascaded GOA units and a control module. Each of the GOA units is driven by a first level of transfer clock, a second level of transfer clock, a first control clock and a second control clock to charge horizontal signal lines corresponding to a display area. The control module masks the first level of transfer clock and the second level of transfer clock when all of the horizontal signal lines are charged completely by the GOA circuit, such that the gate driving signals on the horizontal signal lines are discharged until the level equals to the predetermined level. In this way, the horizontal signal lines are prevented from generating redundant pulse signals before the first gate driving signals are outputted, which ensures the normal operations of the GOA circuit.
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