公开(公告)号：US20230270022A1

公开(公告)日：2023-08-24

申请号：US18310361

申请日：2023-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/841 ,  H10B63/30 ,  H10N70/021 ,  H10N70/061 ,  H10N70/826 ,  G11C2213/79 ,  G11C13/003

Abstract: A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.

公开(公告)号：US20230261070A1

公开(公告)日：2023-08-17

申请号：US18305636

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei Fang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823475 ,  H01L21/823431 ,  H01L29/7851 ,  H01L27/0886

Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

公开(公告)号：US20230253314A1

公开(公告)日：2023-08-10

申请号：US18135563

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu CHEN ,  Chung-Liang CHENG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L21/02592 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/535 ,  H01L23/53266

Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.

公开(公告)号：US20230065446A1

公开(公告)日：2023-03-02

申请号：US17463402

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L27/12

Abstract: A semiconductor device includes a substrate, a gate all around (GAA) device overlying the substrate, and a thin film transistor (TFT) overlying the GAA device, and a passive device overlying the TFT. The substrate, the GAA device, the TFT, and the passive device is subsequently stacked on each other and at least partially overlap with each other. A via includes a first end, a second end, and a middle portion of the via that is located between the first end and the second end of the via. The first end of the via is connected to the passive device and the second end of the via is connected to one layer of the GAA device. The middle portion of the via is laterally spaced apart from the TFT and the passive device.

公开(公告)号：US20220367621A1

公开(公告)日：2022-11-17

申请号：US17815999

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu CHEN ,  Chung-Liang CHENG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.

公开(公告)号：US20220310638A1

公开(公告)日：2022-09-29

申请号：US17472479

申请日：2021-09-10

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chung-Liang CHENG ,  Huang-Lin CHAO

IPC: H01L27/11514 ,  H01L27/11504 ,  H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L27/11587 ,  H01L27/11597

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

公开(公告)号：US20220190153A1

公开(公告)日：2022-06-16

申请号：US17683260

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei Fang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device includes forming first and second nanostructured layers arranged in an alternating configuration on a substrate, forming first and second nanostructured channel regions in the first nanostructured layers, forming first and second gate-all-around structures wrapped around each of the first and second nanostructured channel regions. The forming the GAA structures includes depositing first and second gate barrier layers having similar material compositions and work function values on the first and second gate dielectric layers, forming first and second diffusion barrier layers on the first and second gate barrier layers, and doping the first and second gate barrier layers from a dopant source layer through the first and second diffusion barrier layers. The first diffusion barrier layer is thicker than the second diffusion barrier layer and the doped first and second gate barrier layers have work function values and doping concentrations different from each other.

公开(公告)号：US20210335616A1

公开(公告)日：2021-10-28

申请号：US17370684

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Ying LIN ,  Cheng-Yi WU ,  Alan TU ,  Chung-Liang CHENG ,  Li-Hsuan CHU ,  Ethan HSIAO ,  Hui-Lin SUNG ,  Sz-Yuan HUNG ,  Sheng-Yung LO ,  C.W. CHIU ,  Chih-Wei HSIEH ,  Chin-Szu LEE

IPC: H01L21/285 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L29/417

Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.

公开(公告)号：US20210328018A1

公开(公告)日：2021-10-21

申请号：US17360451

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

公开(公告)号：US20210098589A1

公开(公告)日：2021-04-01

申请号：US16589957

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L29/49 ,  H01L21/8234

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate, patterning the first semiconductor layers and the second semiconductor layers into a fin structure, removing the first semiconductor layers of the fin structure thereby forming gaps between the second semiconductor layers of the fin structure, forming a gate dielectric layer wrapping around the second semiconductor layers, forming a barrier material on the gate dielectric layer. At least a portion of the barrier material is oxidized to form a first barrier oxide. The method for forming the semiconductor structure also includes etching away the first barrier oxide, forming a work function layer to wrap around the second semiconductor layers, and forming a metal fill layer over the work function layer.