公开(公告)号：US11302798B2

公开(公告)日：2022-04-12

申请号：US16888138

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

Abstract: A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids.

公开(公告)号：US20210351034A1

公开(公告)日：2021-11-11

申请号：US17379161

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan Lee ,  Hsin-Yen Huang ,  Yung-Hsu Wu ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/522

Abstract: A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

公开(公告)号：US10930551B2

公开(公告)日：2021-02-23

申请号：US16455840

申请日：2019-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Chia-Tien Wu ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/52 ,  H01L21/768 ,  H01L29/45 ,  H01L23/528

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

公开(公告)号：US20180033653A1

公开(公告)日：2018-02-01

申请号：US15220461

申请日：2016-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Fang Cheng ,  Shao-Kuan Lee ,  Hai-Ching Chen

IPC: H01L21/67 ,  H01L21/683 ,  H01L21/677

CPC classification number: H01L21/6719 ,  H01L21/67115 ,  H01L21/6715 ,  H01L21/67161 ,  H01L21/67207

Abstract: A processing apparatus includes a spin coating chamber, an ultraviolet curing chamber, a transfer module and an enclosure. The transfer module is assigned with a plurality transfer destinations, in which two of the transfer destinations are respectively located within the spin coating chamber and the ultraviolet curing chamber. The transfer module, the spin coating chamber and the ultraviolet curing chamber are enclosed by the enclosure.

公开(公告)号：US09568677B2

公开(公告)日：2017-02-14

申请号：US13905404

申请日：2013-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Hai-Ching Chen ,  Tien-I Bao

IPC: G02B6/136 ,  G02B6/43 ,  G02B6/12

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/43

Abstract: Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface.

Abstract translation: 提供形成波导结构的实施例。 波导结构包括基板，并且基板具有互连区域和波导区域。 波导结构还包括形成在衬底中的沟槽，并且沟槽具有倾斜的侧壁表面和基本平坦的底部。 波导结构还包括形成在基板上的底部包层，并且底部包层从互连区域延伸到波导区域，并且底部包层用作互连区域中的绝缘层。 波导结构还包括形成在倾斜侧壁表面上的底部包层上的金属层。

公开(公告)号：US20140225261A1

公开(公告)日：2014-08-14

申请号：US14258175

申请日：2014-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

IPC: H01L23/485 ,  H01L23/482

CPC classification number: H01L23/4827 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer. The continuous conductive body is made up of a lower body region and an upper body region. The lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body. The second width is less than the first width. A barrier layer separates the continuous conductive body from the dielectric layer.

Abstract translation: 本公开的一些实施例涉及用于连接半导体衬底的器件的互连结构。 所述互连结构包括在所述衬底上的电介质层和穿过所述电介质层的连续导电体。 连续导电体由下体区域和上体区域构成。 下体区域具有限定在连续导电体的相对的下侧壁之间的第一宽度，并且上体区域具有限定在连续导电体的相对的上侧壁之间的第二宽度。 第二宽度小于第一宽度。 阻挡层将连续导电体与电介质层分开。

公开(公告)号：US12176247B2

公开(公告)日：2024-12-24

申请号：US17728295

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Fang Cheng ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC: H01L21/02 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

Abstract: A semiconductor device includes a substrate, a first conductive feature disposed in a top portion of the substrate, a metal containing layer disposed on the first conductive feature, and a second conductive feature disposed on and through the metal containing layer and in physical contact with the first conductive feature. The metal containing layer includes an M-O—X group, M representing a metal atom, O representing an oxygen atom, and X representing an element other than hydrogen.

公开(公告)号：US20240379559A1

公开(公告)日：2024-11-14

申请号：US18780834

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi Yang ,  Yu-Chen Chan ,  Ming-Han Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer. The semiconductor structure includes a first graphene layer disposed over the first conductive feature and a second graphene layer disposed over a portion of the second conductive feature. An etch-stop layer (ESL) is horizontally interposed between the first graphene layer and the second graphene layer. A side surface of the first or the second graphene layer directly contacts a side surface of the ESL. A third conductive feature is electrically coupled to the second conductive feature. The third conductive feature is separated from the first graphene layer by a portion of the ESL, and the third conductive feature also directly contacts a top surface of the ESL.

公开(公告)号：US11935783B2

公开(公告)日：2024-03-19

申请号：US17745614

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

公开(公告)号：US11769815B2

公开(公告)日：2023-09-26

申请号：US17319461

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/417 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L29/516 ,  H01L29/40111 ,  H01L29/41725 ,  H01L29/6656 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/20 ,  H10B51/30

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tuning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.