公开(公告)号：US10713136B2

公开(公告)日：2020-07-14

申请号：US15713557

申请日：2017-09-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu

IPC: G11C29/00 ,  G06F11/20 ,  G11C29/44 ,  G11C8/12

Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.

公开(公告)号：US10133285B2

公开(公告)日：2018-11-20

申请号：US15791226

申请日：2017-10-23

Applicant: QUALCOMM Incorporated

Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

IPC: G05F1/10 ,  G06F1/32 ,  H02M1/32

Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

公开(公告)号：US09940987B2

公开(公告)日：2018-04-10

申请号：US15070963

申请日：2016-03-15

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Po-Hung Chen ,  David Li ,  Sei Seung Yoon

IPC: G11C7/00 ,  G11C8/08 ,  G11C8/10 ,  G11C8/06 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C8/06 ,  G11C8/10

Abstract: A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.

公开(公告)号：US09865337B1

公开(公告)日：2018-01-09

申请号：US15466749

申请日：2017-03-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Mukund Narasimhan ,  Raghav Gupta ,  Pradeep Raj ,  Rahul Sahu ,  Po-Hung Chen ,  Chulmin Jung

IPC: G11C5/10 ,  G11C11/419 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/417

Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.

公开(公告)号：US09851730B2

公开(公告)日：2017-12-26

申请号：US14684128

申请日：2015-04-10

Applicant: QUALCOMM Incorporated

Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

IPC: G05F1/10 ,  G06F1/32 ,  H02M1/32

CPC classification number: G05F1/10 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3287 ,  G06F1/329 ,  H02M1/32

Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.

公开(公告)号：US09640231B1

公开(公告)日：2017-05-02

申请号：US15014830

申请日：2016-02-03

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Chulmin Jung

IPC: G11C7/00 ,  G11C7/06 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/222 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/002

Abstract: A sense amplifier (SA) and a method for operating the SA are provided. The SA includes a first differential pair of transistors configured to receive a first differential input, a second differential pair of transistors configured to receive a second differential input, and a current source configured to source a current to flow through the first and second differential pairs of transistors. The method includes receiving by a first differential pair of transistors a first differential input, receiving by a second differential pair of transistors a second differential input, and flowing a current through the first and second differential pairs of transistors. A multi-bank memory is provided. The memory includes a first bank of memory cells and a second bank of memory cells sharing the disclosed SA.

公开(公告)号：US09401201B1

公开(公告)日：2016-07-26

申请号：US14720383

申请日：2015-05-22

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Fahad Ahmed ,  David Li ,  Sei Seung Yoon

IPC: G11C11/41 ,  G11C11/419 ,  G11C5/14 ,  G11C11/413 ,  G11C16/10 ,  G11C16/06 ,  G11C7/12 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/413 ,  G11C13/0069 ,  G11C16/06 ,  G11C16/10

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell configured to be powered from a first voltage source, a bitline, and a write driver configured to write to the memory cell through the bitline, the write driver comprising a pull-up circuit to pull up bitline voltage towards a second voltage source while using the first voltage source to limit the bitline voltage, the first and second voltage sources being in different voltage domains.

Abstract translation: 提供了一种用于操作存储器的存储器和方法。 存储器包括被配置为由第一电压源，位线和写入驱动器供电的存储器单元，配置为通过位线写入存储器单元，写入驱动器包括上拉电路，以将位线电压拉向 第二电压源，同时使用第一电压源来限制位线电压，第一和第二电压源处于不同的电压域。

公开(公告)号：US20150279451A1

公开(公告)日：2015-10-01

申请号：US14227330

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Wuyang Hao ,  Sei Seung Yoon

IPC: G11C11/418

CPC classification number: G11C11/418 ,  G11C8/08

Abstract: A pulse latch is provided that latches a ground signal responsive to decoded signal carried on a decoded signal node. The pulse latch includes a reset logic circuit that controls a switch coupled between the decoded signal node and ground such that when the switch is turned on by the reset logic circuit, the decoded signal node is grounded. The reset of the decoded signal node by the reset logic circuit is responsive to a ground signal. The ground signal is generated so as to be responsive to a clock edge. Thus, the reset of the decoded signal node is also responsive to the clock edge.

Abstract translation: 提供脉冲锁存器，其响应于解码信号节点上承载的解码信号而锁存接地信号。 脉冲锁存器包括复位逻辑电路，其控制耦合在解码信号节点和地之间的开关，使得当开关由复位逻辑电路导通时，解码信号节点接地。 复位逻辑电路对解码信号节点的复位响应于接地信号。 产生接地信号以响应于时钟沿。 因此，解码信号节点的复位也响应时钟边缘。

公开(公告)号：US20140355365A1

公开(公告)日：2014-12-04

申请号：US13910078

申请日：2013-06-04

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Nishith Desai ,  Chulmin Jung

IPC: H03K3/037 ,  G11C7/22

CPC classification number: G11C7/222 ,  G11C8/08

Abstract: Various circuits and methods of operating circuits are disclosed. A circuit may include a pulse generator and a latch having an output configured to trigger the pulse generator, wherein the latch is configured to be set by an input signal and reset by feedback from the pulse generator. A method may include resetting a latch using feedback from a pulse generator by setting a latch using an input signal, triggering a pulse generator using an output from the latch, and resetting the latch using feedback from the pulse generator.

Abstract translation: 公开了各种电路和操作电路的方法。 电路可以包括脉冲发生器和具有被配置为触发脉冲发生器的输出的锁存器，其中锁存器被配置为由输入信号设置并通过来自脉冲发生器的反馈进行复位。 方法可以包括使用来自脉冲发生器的反馈来使用来自脉冲发生器的反馈来重置锁存器，通过使用输入信号设置锁存器，使用来自锁存器的输出触发脉冲发生器，以及使用来自脉冲发生器的反馈来复位锁存器。

公开(公告)号：US08879328B2

公开(公告)日：2014-11-04

申请号：US13837874

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung

IPC: G11C16/28 ,  G11C7/08 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26

CPC classification number: G11C7/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28 ,  G11C29/702 ,  G11C29/848

Abstract: A memory includes a redundant sense amplifier and a plurality of sense amplifier pairs. Each sense amplifier pair includes a first sense amplifier and a second sense amplifier. Each sense amplifier pair drives a common load line. The memory is configured to implement column redundancy using a single redundant sense amplifier without requiring local read lines for each sense amplifier.

Abstract translation: 存储器包括冗余读出放大器和多个读出放大器对。 每个读出放大器对包括第一读出放大器和第二读出放大器。 每个读出放大器对驱动公共负载线。 存储器被配置为使用单个冗余读出放大器实现列冗余，而不需要每个读出放大器的本地读取线。