知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

57 records (took 0.021 seconds)

    TECHNIQUES FOR MULTI-READ AND MULTI-WRITE OF MEMORY CIRCUIT
    51.
    发明申请
    TECHNIQUES FOR MULTI-READ AND MULTI-WRITE OF MEMORY CIRCUIT 审中-公开

    公开(公告)号：US20190198093A1

    公开(公告)日：2019-06-27

    申请号：US16226385

    申请日：2018-12-19

    Applicant: Intel Corporation

    Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

    IPC: G11C11/419 ,  G11C11/412

    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

    Bitcell state retention
    55.
    发明授权
    Bitcell state retention 有权

    公开(公告)号：US09666257B2

    公开(公告)日：2017-05-30

    申请号：US14696050

    申请日：2015-04-24

    Applicant: INTEL CORPORATION

    Inventor： Charles Augustine ,  Shigeki Tomishima ,  James W. Tschanz ,  Shih-Lien L. Lu

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C11/1659 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

    Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

Patent Agency Ranking