公开(公告)号：US11563003B2

公开(公告)日：2023-01-24

申请号：US17248330

申请日：2021-01-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chen Zhang ,  Tenko Yamashita ,  Joshua M. Rubin ,  Brent Anderson

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A method comprising forming at least one fin on a substrate, wherein the at least one fin has a first section and a second section. Forming a separating layer on the substrate to isolate the second section of the fin from the first section of the fin. Forming as first set of electrical components on the first section of the at least one fin. Flipping the substrate over and removing the substrate to expose a surface of the second section of the at least one fin. Removing a portion of the second section of the at least one fin, whereby removing a portion of the second section a trench is created between sections of the separating layer and an exposed portion of the at least one fin and forming a hard mask in the trench.

公开(公告)号：US20220181286A1

公开(公告)日：2022-06-09

申请号：US17115882

申请日：2020-12-09

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Yang Liu ,  Steven Lorenz Wright ,  Paul S. Andry

IPC: H01L23/00 ,  H01L23/538

Abstract: A pillar structure is provided. The pillar structure includes a plurality of pillars. Each of the pillars include a capping material layer formed in a pit etched into a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attach material layer formed on the base layer. The pillars are joined vertically together to form the pillar structure.

公开(公告)号：US20210366789A1

公开(公告)日：2021-11-25

申请号：US16882624

申请日：2020-05-25

Applicant: International Business Machines Corporation

Inventor： John Knickerbocker ,  Bing Dang ,  Qianwen Chen ,  Joshua M. Rubin ,  Arvind Kumar

IPC: H01L21/66 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.

公开(公告)号：US20210265275A1

公开(公告)日：2021-08-26

申请号：US17319772

申请日：2021-05-13

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Steven Lorenz Wright ,  Lawrence A. Clevenger

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/00

Abstract: A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips.

公开(公告)号：US11069679B2

公开(公告)日：2021-07-20

申请号：US16395563

申请日：2019-04-26

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Chen Zhang ,  Kangguo Cheng ,  Tenko Yamashita ,  Joshua M. Rubin

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

公开(公告)号：US10991635B2

公开(公告)日：2021-04-27

申请号：US16517568

申请日：2019-07-20

Applicant: International Business Machines Corporation

Inventor： Dale Curtis McHerron ,  Kamal K. Sikka ,  Joshua M. Rubin ,  Ravi K. Bonam ,  Ramachandra Divakaruni ,  William J. Starke ,  Maryse Cournoyer

IPC: H01L23/538 ,  H01L23/13 ,  H01L27/24 ,  H01L23/532

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

公开(公告)号：US10910312B2

公开(公告)日：2021-02-02

申请号：US16663592

申请日：2019-10-25

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Terence B. Hook

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/06 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L27/088 ,  H01L21/321

Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.

公开(公告)号：US10748901B2

公开(公告)日：2020-08-18

申请号：US16166996

申请日：2018-10-22

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin ,  Nicolas Loubet ,  Terence B. Hook

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L21/768 ,  H01L23/522 ,  H01L21/8238 ,  H01L21/822

Abstract: Devices and methods are provided for fabricating metallic interlayer via contacts within source/drain regions of field-effect transistor devices of a monolithic three-dimensional semiconductor integrated circuit device. For example, a semiconductor integrated circuit device includes a first device layer and a second device layer disposed on the first device layer. The first device layer includes a metallic interconnect structure formed in an insulating layer. The second device layer includes first and second field-effect transistor devices having respective first and second gate structures. A metallic interlayer via contact is disposed between the first and second gate structures in contact with the metallic interconnect structure of the first device layer, wherein a width of the metallic interlayer via contact is defined by a spacing between adjacent sidewalls of the first and second gate structures. Epitaxial source/drain layers for the first and second field-effect transistor devices are embedded within the metallic interlayer via contact.

公开(公告)号：US20200152629A1

公开(公告)日：2020-05-14

申请号：US16741973

申请日：2020-01-14

Applicant: International Business Machines Corporation

Inventor： Joshua M. Rubin

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/033 ,  H01L29/66 ,  H01L29/16 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/822

Abstract: Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins. The first and second vertical semiconductor fins are utilized to fabricate first and second vertical field-effect transistor devices on first and second device layers of a monolithic three-dimensional semiconductor integrated circuit device

公开(公告)号：US10600694B2

公开(公告)日：2020-03-24

申请号：US16010446

申请日：2018-06-16

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Alexander Reznicek ,  Joshua M. Rubin ,  Junli Wang

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/49 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L27/092

Abstract: Gate metal patterning techniques enable the incorporation of different work function metals in CMOS devices such as nanosheet transistor devices, vertical FETs, and FinFETs. Such techniques facilitate removal of gate metal from one region of a device without damage from over-etching to an adjacent region. The fabrication of CMOS devices with adjoining nFET/pFET gate structures and having very tight gate pitch is also facilitated. The techniques further enable the fabrication of CMOS devices with adjoining gate structures that require relatively long etch times for removal of gate metal therefrom, such as nanosheet transistors. A nanosheet transistor device including dual metal gates as fabricated allows tight integration.