公开(公告)号：US20200183849A1

公开(公告)日：2020-06-11

申请号：US16702073

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06T1/60 ,  G06F12/0868 ,  G06F12/0846 ,  G06F12/0806 ,  G06F12/0855 ,  G06F12/0802 ,  G06F12/126

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US10565354B2

公开(公告)日：2020-02-18

申请号：US15482514

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Pattabhiraman K ,  Balaji Vembu ,  Altug Koker

IPC: G06F21/10 ,  G06F9/455 ,  G06F12/0815 ,  G06T15/00 ,  H04N19/00 ,  H04N21/4405

Abstract: An apparatus and method for protecting content in a graphics processor. For example, one embodiment of an apparatus comprises: encode/decode circuitry to decode protected audio and/or video content to generate decoded audio and/or video content; a graphics cache of a graphics processing unit (GPU) to store the decoded audio and/or video content; first protection circuitry to set a protection attribute for each cache line containing the decoded audio and/or video data in the graphics cache; a cache coherency controller to generate a coherent read request to the graphics cache; second protection circuitry to read the protection attribute to determine whether the cache line identified in the read request is protected, wherein if it is protected, the second protection circuitry to refrain from including at least some of the data from the cache line in a response.

公开(公告)号：US20200004329A1

公开(公告)日：2020-01-02

申请号：US16515315

申请日：2019-07-18

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  James M. Holland ,  Pattabhiraman K ,  Sayan Lahiri ,  Radhakrishnan Venkataraman ,  Kamal Sinha ,  Ankur N. Shah ,  Deepak S. Vembar ,  Abhishek R. Appu ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F3/01 ,  G06T15/00 ,  G06T3/40 ,  G06T1/60 ,  G06F3/16 ,  G06F3/147 ,  G06T19/00 ,  G06F3/0481 ,  G06T7/80

Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.

公开(公告)号：US10304421B2

公开(公告)日：2019-05-28

申请号：US15482535

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Jason Tanner ,  Joydeep Ray ,  Altug Koker ,  Abhishek R. Appu ,  Pattabhiraman K

IPC: G09G5/395 ,  G06F3/14 ,  G09G3/00 ,  G09G5/36 ,  G06F9/451 ,  H04N19/42 ,  G06F9/455 ,  G06T1/20 ,  G06T1/60 ,  G06T9/00 ,  G06T15/00

Abstract: An apparatus and method are described for efficiently rendering an transmitting to a remote display. For example, one embodiment of a remote display apparatus comprises: a display engine to render a sequence of video images; an encoder to compress the sequence of video images to generate a sequence of compressed video images; a network interface controller to transmit the compressed video images over a network link to a remote display; a plurality of buffer pointer registers to store read pointers and write pointers identifying read locations and write locations, respectively, in a frame buffer and a compressed stream buffer; a central processing unit (CPU) to initialize the read pointers and write pointers for processing one or more of the video images; and the display engine to access a first write pointer to write to a specified location in the frame buffer, the encoder to begin reading from the frame buffer based on a first read pointer value, the encoder to write to the compressed stream buffer based on a second write pointer value, and the network interface controller to read from the compressed stream buffer based on a second read pointer value, the first and second write and read pointer values to be updated without intervention from the CPU as the display engine writes to the frame buffer, the encoder reads from the frame buffer and writes to the compressed stream buffer, and the network interface controller reads from the compressed stream buffer.

公开(公告)号：US20180299952A1

公开(公告)日：2018-10-18

申请号：US15488666

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  James M. Holland ,  Pattabhiraman K ,  Sayan Lahiri ,  Radhakrishnan Venkataraman ,  Kamal Sinha ,  Ankur N. Shah ,  Deepak S. Vembar ,  Abhishek R. Appu ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F3/01 ,  G06T15/00 ,  G06T3/40 ,  G06T1/60 ,  G06F3/16 ,  G06F3/147

CPC classification number: G06F3/013 ,  G06F3/011 ,  G06F3/016 ,  G06F3/04815 ,  G06F3/147 ,  G06F3/167 ,  G06T1/60 ,  G06T3/40 ,  G06T7/80 ,  G06T15/005 ,  G06T19/006 ,  G06T2200/28

Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.

公开(公告)号：US20250103548A1

公开(公告)日：2025-03-27

申请号：US18948174

申请日：2024-11-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter, JR. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US20250103511A1

公开(公告)日：2025-03-27

申请号：US18905667

申请日：2024-10-03

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC: G06F12/123 ,  G06F12/0875 ,  G06F12/0891 ,  G06T1/60

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

公开(公告)号：US12079155B2

公开(公告)日：2024-09-03

申请号：US17428216

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Selvakumar Panneer ,  Saurabh Tangri ,  Ben Ashbaugh ,  Scott Janus ,  Abhishek Appu ,  Varghese George ,  Ravishankar Iyer ,  Nilesh Jain ,  Pattabhiraman K ,  Altug Koker ,  Mike MacPherson ,  Josh Mastronarde ,  Elmoustapha Ould-Ahmed-Vall ,  Jayakrishna P. S ,  Eric Samson

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

公开(公告)号：US20240232094A1

公开(公告)日：2024-07-11

申请号：US18405933

申请日：2024-01-05

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0868 ,  G06F12/0893 ,  G06F12/126 ,  G06T1/60

CPC classification number: G06F12/0877 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0848 ,  G06F12/0855 ,  G06F12/0868 ,  G06F12/126 ,  G06T1/60 ,  G06F12/0893

Abstract: One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.

公开(公告)号：US11829525B2

公开(公告)日：2023-11-28

申请号：US17233649

申请日：2021-04-19

Applicant: Intel Corporation

Inventor： Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Chandrasekaran Sakthivel ,  Jeffery S. Boles ,  Adam T. Lake ,  James M. Holland ,  Pattabhiraman K ,  Sayan Lahiri ,  Radhakrishnan Venkataraman ,  Kamal Sinha ,  Ankur N. Shah ,  Deepak S. Vembar ,  Abhishek R. Appu ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F3/01 ,  G06T15/00 ,  G06T3/40 ,  G06T1/60 ,  G06F3/16 ,  G06F3/147 ,  G06T19/00 ,  G06F3/04815 ,  G06T7/80

CPC classification number: G06F3/013 ,  G06F3/011 ,  G06F3/016 ,  G06F3/04815 ,  G06F3/147 ,  G06F3/167 ,  G06T1/60 ,  G06T3/40 ,  G06T7/80 ,  G06T15/005 ,  G06T19/006 ,  G06T2200/28

Abstract: Systems, apparatuses and methods may provide away to enhance an augmented reality (AR) and/or virtual reality (VR) user experience with environmental information captured from sensors located in one or more physical environments. More particularly, systems, apparatuses and methods may provide a way to track, by an eye tracker sensor, a gaze of a user, and capture, by the sensors, environmental information. The systems, apparatuses and methods may render feedback, by one or more feedback devices or display device, for a portion of the environment information based on the gaze of the user.