公开(公告)号：US09252138B2

公开(公告)日：2016-02-02

申请号：US14287237

申请日：2014-05-27

Applicant: General Electric Company

Inventor： Gamal Refai-Ahmed ,  David Mulford Shaddock ,  Arun Virupaksha Gowda ,  John Anthony Vogel ,  Christian Giovanniello

IPC: H01L33/02 ,  H01L25/16 ,  H01L25/00 ,  H01L33/62 ,  H01L33/64 ,  H01L33/54 ,  H01S5/022 ,  H01S5/024 ,  H01L23/538

CPC classification number: H01L23/5386 ,  H01L23/49811 ,  H01L33/62 ,  H01L2924/0002 ,  H01S5/02256 ,  H05K3/32 ,  H05K2201/0311 ,  H05K2201/10674 ,  H01L2924/00

Abstract: An electronic packaging assembly having a semiconductor integrated circuit and a plurality of interconnect components is provided. The plurality of interconnect components is operatively coupled to the semiconductor integrated circuit. Further, one or more interconnect components include one or more support elements having a first surface and a second surface, and one or more spring elements having a first end and a second end, and wherein first ends of the one or more spring elements are coupled to the first surface or the second surface of a respective support element.

Abstract translation: 提供一种具有半导体集成电路和多个互连部件的电子封装组件。 多个互连部件可操作地耦合到半导体集成电路。 此外，一个或多个互连部件包括具有第一表面和第二表面的一个或多个支撑元件，以及具有第一端和第二端的一个或多个弹簧元件，并且其中一个或多个弹簧元件的第一端连接 到相应的支撑元件的第一表面或第二表面。

公开(公告)号：US20150380356A1

公开(公告)日：2015-12-31

申请号：US14844515

申请日：2015-09-03

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/538 ,  H01L23/528 ,  H05K1/18 ,  H01L23/367 ,  H01L23/373 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Abstract translation: 封装结构包括介电层，至少一个连接到电介质层的半导体器件，一个或多个施加到电介质层的电介质片和半导体器件，以将半导体器件嵌入其中，并且多个 形成在形成在电介质层和一个或多个电介质层中的至少一个中的半导体器件上的通孔。 封装结构还包括形成在通孔中的金属互连和在封装结构的一个或多个向外表面上以形成与半导体器件的电互连的金属互连。 电介质层由在层压过程中不流动的材料组成，并且所述一个或多个电介质片中的每一个由可固化材料构成，所述可固化材料构造成在层压过程中固化时熔化和流动，以便填充任何空气 半导体器件周围的间隙。

公开(公告)号：US20150194375A1

公开(公告)日：2015-07-09

申请号：US14665735

申请日：2015-03-23

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract translation: 功率覆盖（POL）结构包括POL子模块。 POL子模块包括电介质层和具有附着到电介质层的顶表面的半导体器件。 半导体器件的顶表面具有形成在其上的至少一个接触焊盘。 POL子模块还包括金属互连结构，其延伸穿过介电层并且电耦合到半导体器件的至少一个接触焊盘。 导电垫片耦合到半导体器件的底表面，并且热界面的第一侧耦合到导电垫片。 散热器耦合到电绝缘热接口的第二侧。

公开(公告)号：US08987876B2

公开(公告)日：2015-03-24

申请号：US13897638

申请日：2013-05-20

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/433 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract translation: 功率覆盖（POL）结构包括POL子模块。 POL子模块包括电介质层和具有附着到电介质层的顶表面的半导体器件。 半导体器件的顶表面具有形成在其上的至少一个接触焊盘。 POL子模块还包括金属互连结构，其延伸穿过介电层并且电耦合到半导体器件的至少一个接触焊盘。 导电垫片耦合到半导体器件的底表面，并且热界面的第一侧耦合到导电垫片。 散热器耦合到电绝缘热接口的第二侧。

公开(公告)号：US20140264799A1

公开(公告)日：2014-09-18

申请号：US13897638

申请日：2013-05-20

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract translation: 功率覆盖（POL）结构包括POL子模块。 POL子模块包括电介质层和具有附着到电介质层的顶表面的半导体器件。 半导体器件的顶表面具有形成在其上的至少一个接触焊盘。 POL子模块还包括金属互连结构，其延伸穿过介电层并且电耦合到半导体器件的至少一个接触焊盘。 导电垫片耦合到半导体器件的底表面，并且热界面的第一侧耦合到导电垫片。 散热器耦合到电绝缘热接口的第二侧。

公开(公告)号：US11177204B2

公开(公告)日：2021-11-16

申请号：US16448691

申请日：2019-06-21

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Nancy Cecelia Stoffel ,  Risto Ilkka Tuominen

IPC: H01L21/48 ,  H01L23/08 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L23/055 ,  H01L23/04 ,  H01L23/15 ,  H01L23/538

Abstract: An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.

公开(公告)号：US10700035B2

公开(公告)日：2020-06-30

申请号：US15343261

申请日：2016-11-04

Applicant: General Electric Company

Inventor： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L23/498

Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a bottom surface of the insulating substrate, and a first conductor layer formed adjacent the bottom surface of the insulating substrate. The electronics package also includes a second conductor layer formed on a top surface of the insulating substrate and extending through a plurality of vias in the insulating substrate to electrically couple with the first electrical component and the first conductor layer. A second electrical component is electrically coupled to the first conductor layer and the first electrical component and the second electrical component are positioned in a stacked arrangement.

公开(公告)号：US10607957B2

公开(公告)日：2020-03-31

申请号：US15729889

申请日：2017-10-11

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/00 ,  H01L23/34 ,  H01L23/538 ,  H05K3/30 ,  H05K3/46 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L25/10 ,  H01L23/42 ,  H01L23/433 ,  H05K1/18 ,  H05K1/02 ,  H05K3/36

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

公开(公告)号：US10607929B2

公开(公告)日：2020-03-31

申请号：US16229049

申请日：2018-12-21

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Kaustubh Ravindra Nagarkar ,  Arun Virupaksha Gowda ,  James Wilson Rose

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H01L23/538

Abstract: An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.

公开(公告)号：US10141251B2

公开(公告)日：2018-11-27

申请号：US14580269

申请日：2014-12-23

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Risto Ilkka Tuominen

IPC: H05K7/00 ,  H01L23/498 ,  H01L23/00 ,  H01L21/66

Abstract: An electronic package is provided. The electronic package includes a substrate and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer disposed on at least a portion of the metal built-up layer. Moreover, the electronic package includes a second conductive layer disposed on the first conductive layer, where the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.