THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20240006516A1

    公开(公告)日:2024-01-04

    申请号:US18321433

    申请日:2023-05-22

    Abstract: An embodiment of the inventive concept provides a thin film transistor and a manufacturing method of the same. The manufacturing method includes forming a data electrode on one side of a substrate, forming a spacer layer on a portion of the data electrode and the other side of the substrate, forming a drain electrode on a top surface of the spacer layer, forming an active layer on a sidewall of the spacer layer, the drain electrode, and the data electrode, forming a gate insulation film that covers the active layer on the sidewall of the spacer layer, and forming a doped layer on the gate insulation film and the active layer outside the gate insulation film to form impurity regions at both sides, respectively, of the active layer.

    LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR OPERATING THE SAME

    公开(公告)号:US20230280620A1

    公开(公告)日:2023-09-07

    申请号:US18084203

    申请日:2022-12-19

    Abstract: Provided is a liquid crystal display device and a method for operating the liquid crystal display device. In the liquid crystal display device including a plurality of pixels, one pixel of the plurality of pixels includes a first sub pixel and a second sub pixel, which are adjacent to each other. The one pixel includes a first substrate, a first electrode provided on the first substrate, metamaterial layers provided on the first electrode, wherein the metamaterial layers include a first metamaterial layer within the first sub pixel and a second metamaterial layer within the second sub pixel, a liquid crystal layer provided on the first and second metamaterial layers, a second electrode provided on the liquid crystal layer, and a second substrate provided on the second electrode. The first and second metamaterial layers include metamaterials having properties different from each other, respectively.

    DISPLAY DEVICE
    57.
    发明申请

    公开(公告)号:US20210096434A1

    公开(公告)日:2021-04-01

    申请号:US16987982

    申请日:2020-08-07

    Abstract: Provided is a display device. The display device includes first to second gate lines provided on a substrate having first and second pixel areas and extending in a first direction, first to third data lines extending in a second direction perpendicular to the first direction and intersecting the first to second gate lines, and a first reflective electrode provided inside the first pixel area and a second reflective electrode provided inside the second pixel area, from a planar viewpoint, wherein the first to second gate lines and the first to third data lines define the first pixel area and the second pixel area, wherein the first to second gate lines are spaced apart from each other in the second direction, wherein the first to third data lines are spaced apart from each other in the first direction.

    PIXEL CIRCUIT FOR CONFIGURING ACTIVE INPUT ARRAY AND INPUT DEVICE INCLUDING THE SAME

    公开(公告)号:US20200072665A1

    公开(公告)日:2020-03-05

    申请号:US16552550

    申请日:2019-08-27

    Abstract: Provided is a pixel circuit. The pixel circuit includes a conversion element configured to form a voltage of an input level corresponding to a magnitude of a received energy at a first node, a first transistor configured to adjust the voltage of the first node to a first level in response to a first signal received at a first time interval, a first capacitive element configured to form a voltage at a second node based on the voltage of the first node, a second transistor configured to adjust a level of the voltage of the second node to a second level in response to the first signal, a third transistor configured to form a voltage at a third node, the voltage having a level corresponding to the level of the voltage of the second node, a fourth transistor configured to output a current corresponding to the voltage of the third node in response to a second signal received in a second time interval after the first time interval, and a fifth transistor configured to adjust the voltage of the third node to a third level in response to a third signal received in a third time interval after the second time interval.

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