DISPLAY DEVICE
    2.
    发明公开
    DISPLAY DEVICE 审中-公开

    公开(公告)号:US20240057436A1

    公开(公告)日:2024-02-15

    申请号:US18315314

    申请日:2023-05-10

    CPC classification number: H10K59/38 H10K59/873 H10K59/879 H10K59/353

    Abstract: Disclosed is a display device. An embodiment of the inventive concept provides a display device that includes a substrate including a first sub pixel region, a second sub pixel region, and a third sub pixel region, reflective bottom electrodes provided on the substrate, a blue light emitting layer provided on the lower reflective electrodes, an encapsulation layer provided on the blue light emitting layer, a green color conversion layer provided on the encapsulation layer in the first sub pixel region, a color conversion layer provided on the encapsulation layer in the second sub pixel region, a blue reflective layer provided on both the green color conversion layer and the color conversion layer, and a blue transmissive layer disposed adjacent to the color conversion layer and provided on the encapsulation layer in the third sub pixel region.

    DISPLAY DEVICE
    6.
    发明申请

    公开(公告)号:US20220199706A1

    公开(公告)日:2022-06-23

    申请号:US17525245

    申请日:2021-11-12

    Abstract: Provided is a display device. The display device includes a substrate having a pixel area including a first sub-pixel area, a second sub-pixel area, and a third sub-pixel area, a first control layer on the substrate, a second control layer on the first control layer, an intervening layer disposed between the first control layer and the second control layer on the first sub-pixel area and the second sub-pixel area, first quantum dots on the intervening layer of the first sub-pixel area, second quantum dots on the intervening layer of the second sub-pixel area, and an organic layer configured to cover a top surface and a side surface of the intervening layer between the first control layer and the second control layer.

    DISPLAY PANEL
    7.
    发明申请

    公开(公告)号:US20250107337A1

    公开(公告)日:2025-03-27

    申请号:US18618163

    申请日:2024-03-27

    Abstract: Provided is a display panel including a base substrate, a display element layer, and a light control layer, wherein the display element layer includes a first electrode, a second electrode, a light-emitting layer and a first pixel definition layer, the light control layer includes a second pixel definition layer, and a light control pattern including quantum dots, a bottom surface of the first pixel definition layer has a first width in a first direction, the first pixel definition layer has a first height in a second direction, a bottom surface of the second pixel definition layer has a second width in the first direction, the second pixel definition layer has a second height in the second direction, and a first aspect ratio calculated by dividing the first height by the first width is smaller than a second aspect ratio calculated by dividing the second height by the second width.

    PIXEL CIRCUIT FOR CONFIGURING ACTIVE INPUT ARRAY AND INPUT DEVICE INCLUDING THE SAME

    公开(公告)号:US20200072665A1

    公开(公告)日:2020-03-05

    申请号:US16552550

    申请日:2019-08-27

    Abstract: Provided is a pixel circuit. The pixel circuit includes a conversion element configured to form a voltage of an input level corresponding to a magnitude of a received energy at a first node, a first transistor configured to adjust the voltage of the first node to a first level in response to a first signal received at a first time interval, a first capacitive element configured to form a voltage at a second node based on the voltage of the first node, a second transistor configured to adjust a level of the voltage of the second node to a second level in response to the first signal, a third transistor configured to form a voltage at a third node, the voltage having a level corresponding to the level of the voltage of the second node, a fourth transistor configured to output a current corresponding to the voltage of the third node in response to a second signal received in a second time interval after the first time interval, and a fifth transistor configured to adjust the voltage of the third node to a third level in response to a third signal received in a third time interval after the second time interval.

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