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    Method and circuit for controlling a precharge cycle of a memory device
    51.
    发明授权
    Method and circuit for controlling a precharge cycle of a memory device 失效
    用于控制存储器件的预充电循环的方法和电路

    公开(公告)号：US5828612A

    公开(公告)日：1998-10-27

    申请号：US958646

    申请日：1997-10-27

    申请人： Ruey J. Yu ,  Paul William Hollis ,  Renny Lee Eisele

    发明人： Ruey J. Yu ,  Paul William Hollis ,  Renny Lee Eisele

    IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419 ,  G11C7/12

    摘要： A method and circuit for optimally controlling memory array bit line precharge timing to increase memory frequency of operation by generating a precharge output (110) for memory array bit lines in response to the earliest asserted control input among precharge control inputs. A write precharge signal (218) early enables a write precharge operation by enabling the precharge signal (110) a delayed period after an enabling falling dock edge of clock (104), as indicated by a write precharge enable signal (210), and during a write cycle, as indicated by a write precharge trigger (212). Thereafter, a default precharge trigger (216) is enabled to ensure that write precharging operation continues for an extended and optimal duration. A read precharge trigger (214) enables precharging after a read operation by enabling the precharge signal (110) in close proximity to the disabling of read sense amplifiers within the memory array to enhance post-read precharging. Thereafter, the default precharge trigger (216), is enabled to ensure that the read precharging operation continues for an extended and optimal duration.

    摘要翻译： 一种用于最佳地控制存储器阵列位线预充电定时的方法和电路，以响应于预充电控制输入中最早被断言的控制输入产生用于存储器阵列位线的预充电输出（110）来增加操作的存储器频率。 写预充电信号（218）早期通过使能预充电信号（110）在时钟（104）的使能下降沿之后的延迟时段（如由写预充电使能信号（210）所指示）和在 写周期，如由写预充电触发器（212）所指示的。 此后，启用默认预充电触发器（216）以确保写入预充电操作持续延长和最佳持续时间。 读取预充电触发器（214）通过使预充电信号（110）非常接近存储器阵列内的读出读出放大器的禁用来实现读取操作之后的预充电，以增强读取后预充电。 此后，启用默认预充电触发器（216），以确保读取的预充电操作持续延长和最佳持续时间。