公开(公告)号：US06818488B2

公开(公告)日：2004-11-16

申请号：US10332451

申请日：2003-09-08

申请人： Olivier Joubert ,  Giles Cunge ,  Johann Foucher ,  David Fuard ,  Marceline Bonvalot ,  Laurent Vallier

发明人： Olivier Joubert ,  Giles Cunge ,  Johann Foucher ,  David Fuard ,  Marceline Bonvalot ,  Laurent Vallier

IPC分类号： H01L21338

CPC分类号： H01L29/4958 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28114 ,  H01L29/42376

摘要： The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps: a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching, b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material, c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.

摘要翻译： 本发明涉及一种用于制造CMOS晶体管结构的栅极的方法，该栅极由在衬底的半导体材料的表面上实现的叠层制成，所述堆叠包括栅极隔离层，栅极材料层和栅极掩模 顺序地，该方法包括以下步骤：a）不被栅极掩模掩蔽的栅极材料层的顶部的各向异性蚀刻，该蚀刻步骤离开栅极材料层的底部并导致形成沉积物 由各向异性腐蚀产生的蚀刻侧面上的蚀刻产物组成，b）处理由蚀刻产物构成的沉积物，以形成对栅极材料的后续蚀刻加强的保护层，c）蚀刻栅极材料的底部 层，直到栅极隔离层，该蚀刻包括栅极材料层的各向同性蚀刻，以使栅极在底部比在顶部更短。

公开(公告)号：US06808970B2

公开(公告)日：2004-10-26

申请号：US10602583

申请日：2003-06-24

申请人： Thomas Feudel ,  Christian Krueger ,  Lutz Herrmann

发明人： Thomas Feudel ,  Christian Krueger ,  Lutz Herrmann

IPC分类号： H01L21338

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/7842

摘要： A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.

摘要翻译： 公开了一种用于制造场效应晶体管的制造工艺，包括在其上制造晶体管的衬底的表面上产生应变表面层。 应变表面层是通过将氙和/或其它重的惰性离子注入衬底而产生的。 可以在栅极氧化物生长之后或之前进行植入。 之后的处理与传统的MOS技术一样进行。 假设应变表面层改善了晶体管的沟道迁移率。

公开(公告)号：US06787408B2

公开(公告)日：2004-09-07

申请号：US09930856

申请日：2001-08-16

申请人： Chien-Wei Chen ,  Jiun-Ren Lai

发明人： Chien-Wei Chen ,  Jiun-Ren Lai

IPC分类号： H01L21338

CPC分类号： H01L27/11517 ,  H01L21/31055 ,  H01L27/115

摘要： A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides. Finally, the mask layer is stripped and then the spacing dielectric layer remains to form the electrical insulating layer on bit lines of the flash memory.

摘要翻译： 公开了一种在闪速存储器的位线上形成电绝缘层的方法。 依次在半导体衬底上形成导电层，掩模层和覆盖层，然后进行蚀刻以形成多个间隔。 之后，在半导体衬底上形成电介质层，然后在电介质层上形成平坦化层。 依次蚀刻平坦化层和电介质层，其中平坦化层的蚀刻速率小于电介质层的蚀刻速率。 接下来，蚀刻电介质层以去除电介质层的一部分，其中电介质层的蚀刻速率高于盖层的蚀刻速率，因此在间隔上形成间隔电介质层。 此后，剥离盖层，其中电介质层的蚀刻速率小于掩模层的蚀刻速率，使得间隔电介质层具有圆顶和倾斜的侧面。 最后，剥离掩模层，然后保留间隔电介质层以在闪存的位线上形成电绝缘层。

公开(公告)号：US06784035B2

公开(公告)日：2004-08-31

申请号：US10342590

申请日：2003-01-15

申请人： John P. Snyder ,  John M. Larson

发明人： John P. Snyder ,  John M. Larson

IPC分类号： H01L21338

CPC分类号： H01L29/0847 ,  H01L21/28194 ,  H01L21/823412 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/47 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/7839

摘要： The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

摘要翻译： 本发明是具有应变半导体衬底和肖特基势垒源极和漏极的场效应晶体管及其制造方法。 与传统器件相比，肖特基势垒场效应晶体管的体电荷载流子传输特性使载流子表面散射最小化，这使得应变衬底能够在该器件中提供改进的功率和速度性能特性。

公开(公告)号：US06780694B2

公开(公告)日：2004-08-24

申请号：US10338930

申请日：2003-01-08

申请人： Bruce B. Doris ,  Omer H. Dokumaci ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Bruce B. Doris ,  Omer H. Dokumaci ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L21338

CPC分类号： H01L21/28114 ,  H01L21/26586 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665

摘要： A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate. Form silicide layers on top of the T-shaped gate electrode and above the source/drain regions.

摘要翻译： 制造半导体晶体管器件的方法包括以下步骤。 提供其上具有栅极介电层的半导体衬底和形成在栅极电介质层上的下部栅极电极结构，而下部栅电极结构具有较低的栅极顶部。 在栅极电介质层上形成平坦化层，离开下部栅电极结构的栅极顶部。 在下栅极电极结构上形成上栅极结构，形成具有上栅极表面的暴露下表面和暴露的栅电极垂直侧壁的T形栅电极。 取出平坦化层。 衬底中形成源/漏极扩展，防止短沟道效应。 形成邻近上部栅极的暴露的下表面和T形栅电极的暴露的垂直侧壁的侧壁间隔物。 在衬底中形成源/漏区。 在T形栅电极的顶部和源极/漏极区之上形成硅化物层。

公开(公告)号：US06777278B2

公开(公告)日：2004-08-17

申请号：US10374438

申请日：2003-02-25

申请人： Richard Peter Smith

发明人： Richard Peter Smith

IPC分类号： H01L21338

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/7783

摘要： High electron mobility transistors (HEMTs) and methods of fabricating HEMTs are provided Devices according to embodiments of the present invention include a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on the channel layer. A first ohmic contact is provided on the barrier layer-to provide a source electrode and a second ohmic contact is also provided on the barrier layer and is spaced apart from the source electrode to provide a drain electrode. A GaN-based cap segment is provided on the barrier layer between the source electrode and the drain electrode. The GaN-based cap segment has a first sidewall adjacent and spaced apart from the source electrode and may have a second sidewall adjacent and spaced apart from the drain electrode. A non-ohmic contact is provided on the GaN-based cap segment to provide a gate contact. The gate contact has a first sidewall which is substantially aligned with the first sidewall of the GaN-based cap segment. The gate contact extends only a portion of a distance between the first sidewall and the second sidewall of the GaN-based cap segment.

摘要翻译： 提供高电子迁移率晶体管（HEMT）和制造HEMT的方法提供根据本发明实施例的器件包括沟道层上的氮化镓（GaN）沟道层和氮化镓（AlGaN）阻挡层。 第一欧姆接触提供在阻挡层上 - 以提供源电极，并且第二欧姆接触还设置在阻挡层上并且与源电极间隔开以提供漏电极。 在源电极和漏电极之间的阻挡层上设置GaN基帽段。 GaN基帽段具有与源电极相邻并间隔开的第一侧壁，并且可以具有与漏电极相邻并间隔开的第二侧壁。 在GaN基帽部分上提供非欧姆接触以提供栅极接触。 栅极触点具有基本上与GaN基帽段的第一侧壁对准的第一侧壁。 栅极接触仅延伸GaN基帽段的第一侧壁和第二侧壁之间的距离的一部分。

公开(公告)号：US06777277B2

公开(公告)日：2004-08-17

申请号：US10205605

申请日：2002-07-26

申请人： Tetsuro Asano ,  Katsuaki Onoda ,  Yoshibumi Nakajima ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Koichi Hirata ,  Mikito Sakakibara ,  Hidetoshi Ishihara

发明人： Tetsuro Asano ,  Katsuaki Onoda ,  Yoshibumi Nakajima ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Koichi Hirata ,  Mikito Sakakibara ,  Hidetoshi Ishihara

IPC分类号： H01L21338

CPC分类号： H01L29/66143 ,  H01L24/05 ,  H01L29/872 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2224/4847 ,  H01L2924/14 ,  H01L2924/00

摘要： A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

摘要翻译： 肖特基势垒二极管具有形成在设置在GaAs衬底上的n外延层中的肖特基接触区域和围绕肖特基接触区域的欧姆电极。 欧姆电极直接设置在形成在基板上的杂质注入区域上。 通过n外延层形成绝缘区域，使得阳极接合焊盘在阴极电压下与器件的其它元件隔离。 该器件的平面结构不包括传统的聚酰亚胺层，因此具有比常规器件更好的高频特性。

公开(公告)号：US06759287B2

公开(公告)日：2004-07-06

申请号：US10435270

申请日：2003-05-07

申请人： Kwan-Ju Koh

发明人： Kwan-Ju Koh

IPC分类号： H01L21338

CPC分类号： H01L29/66583 ,  H01L21/2652 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device is provided that comprises a gate oxide film, a gate electrode, a nitride film, a low concentration impurity area, and a high concentration impurity are. The gate oxide film is formed on a semiconductor substrate. The gate electrode is formed on a predetermined region of the gate oxide film, and an upper portion thereof is wider than a lower portion thereof by a predetermined width. The nitride film is formed at a side of the lower portion of the gate electrode, and a width of the nitride film is equal to the predetermined width. The low concentration impurity area is formed within the semiconductor substrate except at a portion thereof under the lower portion of the gate electrode. The high concentration impurity area is formed within the semiconductor substrate except at a portion thereof under the lower portion of the gate electrode.

摘要翻译： 提供一种半导体器件，其包括栅极氧化膜，栅极电极，氮化物膜，低浓度杂质区域和高浓度杂质。 栅极氧化膜形成在半导体衬底上。 栅电极形成在栅极氧化膜的预定区域上，其上部比其下部宽一定宽度。 氮化物膜形成在栅电极的下部的一侧，氮化膜的宽度等于预定宽度。 低浓度杂质区域形成在半导体衬底中，除了栅电极下部的部分之外。 高浓度杂质区域形成在半导体衬底之外，除了栅电极下部的部分之外。

公开(公告)号：US06716689B2

公开(公告)日：2004-04-06

申请号：US10274035

申请日：2002-10-21

申请人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Sang-Su Kim ,  Jung-Il Lee

发明人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Sang-Su Kim ,  Jung-Il Lee

IPC分类号： H01L21338

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

摘要： A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

公开(公告)号：US06664642B2

公开(公告)日：2003-12-16

申请号：US10075246

申请日：2002-02-15

申请人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

发明人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

IPC分类号： H01L21338

CPC分类号： H01L23/562 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/585 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.