公开(公告)号：US06326302B1

公开(公告)日：2001-12-04

申请号：US09505448

申请日：2000-02-16

申请人： Olivier Joubert ,  David Fuard

发明人： Olivier Joubert ,  David Fuard

IPC分类号： H01L214763

CPC分类号： H01L21/7681 ,  H01L21/31138

摘要： A process for the anisotropic etching of a dielectric organic polymer material using a plasma is provided. The gas phase of the plasma may include a gas mixture of O2/NH3, O2/H2O, O2/CH4 or O2/H2. The oxygen concentration of the gas mixture may be less than 40% by volume. The process may include the fabrication of metal interconnects in a damascene-type structure of an integrated circuit.

摘要翻译： 提供了使用等离子体对介电有机聚合物材料进行各向异性蚀刻的方法。 等离子体的气相可以包括O 2 / NH 3，O 2 / H 2 O，O 2 / CH 4或O 2 / H 2的气体混合物。 气体混合物的氧浓度可以小于40体积％。 该方法可以包括在集成电路的镶嵌型结构中制造金属互连。

公开(公告)号：US06818488B2

公开(公告)日：2004-11-16

申请号：US10332451

申请日：2003-09-08

申请人： Olivier Joubert ,  Giles Cunge ,  Johann Foucher ,  David Fuard ,  Marceline Bonvalot ,  Laurent Vallier

发明人： Olivier Joubert ,  Giles Cunge ,  Johann Foucher ,  David Fuard ,  Marceline Bonvalot ,  Laurent Vallier

IPC分类号： H01L21338

CPC分类号： H01L29/4958 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28114 ,  H01L29/42376

摘要： The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps: a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching, b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material, c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.

摘要翻译： 本发明涉及一种用于制造CMOS晶体管结构的栅极的方法，该栅极由在衬底的半导体材料的表面上实现的叠层制成，所述堆叠包括栅极隔离层，栅极材料层和栅极掩模 顺序地，该方法包括以下步骤：a）不被栅极掩模掩蔽的栅极材料层的顶部的各向异性蚀刻，该蚀刻步骤离开栅极材料层的底部并导致形成沉积物 由各向异性腐蚀产生的蚀刻侧面上的蚀刻产物组成，b）处理由蚀刻产物构成的沉积物，以形成对栅极材料的后续蚀刻加强的保护层，c）蚀刻栅极材料的底部 层，直到栅极隔离层，该蚀刻包括栅极材料层的各向同性蚀刻，以使栅极在底部比在顶部更短。