公开(公告)号：US06734107B2

公开(公告)日：2004-05-11

申请号：US10170308

申请日：2002-06-12

申请人： Jiun-Ren Lai ,  Chien-Wei Chen

发明人： Jiun-Ren Lai ,  Chien-Wei Chen

IPC分类号： H01L21311

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for forming transistor devices having a reduced pitch. The pitch of the formed devices can be reduced to, e.g., half that of conventional devices by using current photolithography conditions. Since the pitch of the devices can be reduced, the device integration can be increased, resulting in smaller and faster integrated circuits. In a preferred embodiment, a conductive layer, a stop layer, and a polysilicon layer are formed on a substrate. A patterned photoresist layer is formed on the polysilicon layer, and a first polymer layer is formed on surfaces of the photoresist layer. The first polymer layer is used as an etching mask to define the polysilicon layer, the stop layer, and the conductive layer. An oxide layer is formed on the substrate, and then the oxide layer is etched back until the polysilicon layer is exposed. The polysilicon layer is removed, and a second polymer layer is formed on surfaces of the oxide layer. The second polymer layer is used as an etching mask to define the conductive layer. Then, the second polymer layer is removed.

摘要翻译： 一种用于形成具有减小的间距的晶体管器件的方法。 通过使用当前的光刻条件，所形成的器件的间距可以减小到例如常规器件的间距的一半。 由于可以减少器件的间距，可以提高器件集成度，从而导致更小更快的集成电路。 在优选实施例中，在衬底上形成导电层，阻挡层和多晶硅层。 在多晶硅层上形成图案化的光致抗蚀剂层，并且在光致抗蚀剂层的表面上形成第一聚合物层。 第一聚合物层用作蚀刻掩模以限定多晶硅层，阻挡层和导电层。 在衬底上形成氧化物层，然后将氧化层回蚀刻直到多晶硅层露出。 去除多晶硅层，并且在氧化物层的表面上形成第二聚合物层。 第二聚合物层用作蚀刻掩模以限定导电层。 然后，除去第二聚合物层。

公开(公告)号：US06537917B2

公开(公告)日：2003-03-25

申请号：US09803921

申请日：2001-03-13

申请人： Jiun-Ren Lai ,  Chien-Wei Chen

发明人： Jiun-Ren Lai ,  Chien-Wei Chen

IPC分类号： H01L21302

CPC分类号： H01L21/31111 ,  H01L21/3144 ,  H01L21/76229

摘要： This invention relates to a method for fabricating a electrically insulating layer, more particularly, to the method for fabricating a electrically insulating layer by using the different etching rates in etching oxide and etching nitride. The present invention uses the way in different etching rates to etch oxide and nitride. When begin the etching process to fabricating the electrically insulating layer, the etching rate of oxide is higher than the etching rate of nitride. When the oxide layer contacts with the ending point which is situated between the oxide layer and the nitride layer or the nitride oxide layer, the etching rate of nitride is higher than the etching rate of oxide to form the flatter surface of the electrically insulating layer.

公开(公告)号：US06492214B2

公开(公告)日：2002-12-10

申请号：US09683649

申请日：2002-01-29

申请人： Chien-Wei Chen ,  Shin-Yi Tsai ,  Ming-Chung Liang ,  Jiun-Ren Lai

发明人： Chien-Wei Chen ,  Shin-Yi Tsai ,  Ming-Chung Liang ,  Jiun-Ren Lai

IPC分类号： H01L21338

CPC分类号： H01L21/28123 ,  H01L21/76224

摘要： A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.

公开(公告)号：US06787408B2

公开(公告)日：2004-09-07

申请号：US09930856

申请日：2001-08-16

申请人： Chien-Wei Chen ,  Jiun-Ren Lai

发明人： Chien-Wei Chen ,  Jiun-Ren Lai

IPC分类号： H01L21338

CPC分类号： H01L27/11517 ,  H01L21/31055 ,  H01L27/115

摘要： A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides. Finally, the mask layer is stripped and then the spacing dielectric layer remains to form the electrical insulating layer on bit lines of the flash memory.

摘要翻译： 公开了一种在闪速存储器的位线上形成电绝缘层的方法。 依次在半导体衬底上形成导电层，掩模层和覆盖层，然后进行蚀刻以形成多个间隔。 之后，在半导体衬底上形成电介质层，然后在电介质层上形成平坦化层。 依次蚀刻平坦化层和电介质层，其中平坦化层的蚀刻速率小于电介质层的蚀刻速率。 接下来，蚀刻电介质层以去除电介质层的一部分，其中电介质层的蚀刻速率高于盖层的蚀刻速率，因此在间隔上形成间隔电介质层。 此后，剥离盖层，其中电介质层的蚀刻速率小于掩模层的蚀刻速率，使得间隔电介质层具有圆顶和倾斜的侧面。 最后，剥离掩模层，然后保留间隔电介质层以在闪存的位线上形成电绝缘层。

公开(公告)号：US06518103B1

公开(公告)日：2003-02-11

申请号：US10026856

申请日：2001-12-20

申请人： Jiun-Ren Lai

发明人： Jiun-Ren Lai

IPC分类号： H01L2100

CPC分类号： H01L27/11568 ,  H01L21/31116

摘要： A method for fabricating a NROM is described, in which a bottom anti-reflective coating (BARC) and a photoresist pattern are sequentially formed on a substrate that has a charge trapping layer formed thereon. An etching process is then performed to pattern the BARC and the charge trapping layer with the photoresist pattern as a mask. The etching process is conducted in an etching chamber equipped with a source power supply and a bias power supply, which two have a power ratio of 1.5˜3, while an etchant used therein is a gas plasma containing trifluoromethane (CHF3) and tetrafluoromethane (CF4). Thereafter, a buried drain is formed in the substrate, a buried drain oxide layer is formed on the buried drain, and then plural gates are formed on the substrate.

摘要翻译： 描述了制造NROM的方法，其中底部抗反射涂层（BARC）和光致抗蚀剂图案依次形成在其上形成有电荷捕获层的基板上。 然后进行蚀刻处理以将光致抗蚀剂图案作为掩模对BARC和电荷俘获层进行图案化。 蚀刻工艺在配备有源电源和偏置电源的蚀刻室中进行，两者的功率比为1.5〜3，其中使用的蚀刻剂是含有三氟甲烷（CHF 3）和四氟甲烷（CF 4）的气体等离子体 ）。 此后，在衬底中形成掩埋漏极，在漏极漏极上形成掩埋漏极氧化层，然后在衬底上形成多个栅极。

公开(公告)号：US06548385B1

公开(公告)日：2003-04-15

申请号：US10170285

申请日：2002-06-12

申请人： Jiun-Ren Lai

发明人： Jiun-Ren Lai

IPC分类号： H01L2122

CPC分类号： H01L21/0337 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/2815 ,  H01L21/32139 ,  H01L21/823437

摘要： A method is described which may be used to reduce a pitch between conductive features. One embodiment of the method involves forming a structure including a substrate, a conductive layer on the substrate, multiple photoresist features arranged on the conductive layer, a polymer layer on top surfaces and sidewalls of each of the photoresist features, and a material layer on and around the photoresist features and the polymer layers. An upper portion of the material layer is removed such that upper surfaces of the photoresist features and the polymer layer are exposed, and a remaining portion of the material layer remains. The polymer layer is removed, and the photoresist features and the remaining portion of the material layer are used as etch masks to pattern the conductive layer, thereby producing a number of conductive features. The photoresist features and the remaining portion of the material layer are removed.

摘要翻译： 描述了可以用于减小导电特征之间的间距的方法。 该方法的一个实施方案包括形成包括基底，基底上的导电层，布置在导电层上的多个光致抗蚀剂特征，每个光致抗蚀剂特征的顶表面和侧壁上的聚合物层以及其上的材料层 围绕光刻胶特征和聚合物层。 去除材料层的上部，使得光致抗蚀剂特征和聚合物层的上表面被暴露，并且剩余的材料层部分残留。 去除聚合物层，并且将光致抗蚀剂的特征和材料层的剩余部分用作蚀刻掩模以对导电层进行图案化，从而产生许多导电特征。 光刻胶的特征和材料层的剩余部分被去除。

公开(公告)号：US20050020043A1

公开(公告)日：2005-01-27

申请号：US10627115

申请日：2003-07-25

申请人： Jiun-Ren Lai

发明人： Jiun-Ren Lai

IPC分类号： H01L21/8238 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823857 ,  H01L21/823828

摘要： A method for forming a semiconductor device having a reduced pitch is provided. A pad oxide layer is formed on a substrate, and a silicon nitride layer is formed on the pad oxide layer. A trimmed photoresist layer is formed on the silicon nitride layer, and the silicon nitride layer is etched using the trimmed photoresist layer as an etch mask. The trimmed photoresist layer is removed until the silicon nitride layer is completely exposed, and an exposed portion of the pad oxide layer is removed until a portion of the substrate is exposed. A gate oxide layer is formed on the exposed portion of the substrate. A poly layer is deposited on the silicon nitride layer, and the poly layer is etched back to form a plurality of poly gates. Then, the silicon nitride layer is removed.

摘要翻译： 提供了一种用于形成具有减小的间距的半导体器件的方法。 在衬底上形成衬垫氧化物层，并且在衬垫氧化物层上形成氮化硅层。 在氮化硅层上形成修整的光致抗蚀剂层，并且使用修整的光致抗蚀剂层作为蚀刻掩模来蚀刻氮化硅层。 去除修整的光致抗蚀剂层直到氮化硅层完全暴露，并且去除衬垫氧化物层的暴露部分，直到暴露出衬底的一部分。 在衬底的暴露部分上形成栅氧化层。 多晶硅层沉积在氮化硅层上，多层被回蚀以形成多个多晶硅栅极。 然后，去除氮化硅层。

公开(公告)号：US06849526B2

公开(公告)日：2005-02-01

申请号：US10708210

申请日：2004-02-17

申请人： Jiun-Ren Lai ,  Chun-Yi Yang ,  Shi-Xian Chen ,  Gwen Chang

发明人： Jiun-Ren Lai ,  Chun-Yi Yang ,  Shi-Xian Chen ,  Gwen Chang

IPC分类号： H01L21/768 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/112 ,  H01L27/115 ,  H01L21/425

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

摘要翻译： 一种掩埋位线及其制造方法，其中，所述器件包括衬底，设置在衬底中的浅掺杂区域，在所述浅掺杂区域的一部分下方设置在所述衬底中的深掺杂区域，其中所述浅掺杂区域和 深色掺杂区域一起形成存储器件的位线。

公开(公告)号：US06720629B2

公开(公告)日：2004-04-13

申请号：US10065351

申请日：2002-10-08

申请人： Jiun-Ren Lai ,  Chun-Yi Yang ,  Shi-Xian Chen ,  Gwen Chang

发明人： Jiun-Ren Lai ,  Chun-Yi Yang ,  Shi-Xian Chen ,  Gwen Chang

IPC分类号： H01L2976

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

摘要翻译： 一种掩埋位线及其制造方法，其中，所述器件包括衬底，设置在衬底中的浅掺杂区域，在所述浅掺杂区域的一部分下方设置在所述衬底中的深掺杂区域，其中所述浅掺杂区域和 深色掺杂区域一起形成存储器件的位线。