公开(公告)号：US08549444B2

公开(公告)日：2013-10-01

申请号：US12101441

申请日：2008-04-11

Applicant: John Richard Dangler ,  Matthew Stephen Doyle

Inventor： John Richard Dangler ,  Matthew Stephen Doyle

IPC: G06F17/50 ,  H05K1/00 ,  H05K1/03

CPC classification number: H05K1/024 ,  H01P11/003 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09881 ,  H05K2203/063

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.

Abstract translation: 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 现有技术的设计和制造工艺现在将物理电介质厚度变化引入到多层横截面中。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了多层结构和制造方法。

公开(公告)号：US20130168145A1

公开(公告)日：2013-07-04

申请号：US13626896

申请日：2012-09-26

Applicant: YING-TSO LAI ,  HSIAO-YUN SU

Inventor： YING-TSO LAI ,  HSIAO-YUN SU

IPC: H01G4/005 ,  H05K1/16

CPC classification number: H01G4/012 ,  H01G4/228 ,  H01G4/33 ,  H01G4/38 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09672

Abstract: A capacitor includes at least two electrode layers opposite to each other and a dielectric layer positioned between the at least two electrode layers. The at least two electrode layers have opposite polarities. Each electrode layer includes a positive electrode and a negative electrode. The positive electrode includes a plurality of first coupling portions spaced substantially evenly and arranged in parallel. The negative electrode includes a plurality of second coupling portions spaced substantially evenly and arranged in parallel. The positive electrode and the negative electrode of each electrode layer are coplanar, and the plurality of first coupling portions interlace with the plurality of second coupling portions.

Abstract translation: 电容器包括彼此相对的至少两个电极层和位于所述至少两个电极层之间的电介质层。 至少两个电极层具有相反的极性。 每个电极层包括正极和负极。 正电极包括大致均匀间隔开并且平行布置的多个第一耦合部分。 负极包括大致均匀间隔开并且平行布置的多个第二联接部。 每个电极层的正电极和负电极是共面的，并且多个第一耦合部分与多个第二耦合部分交织。

公开(公告)号：US08450613B2

公开(公告)日：2013-05-28

申请号：US12659291

申请日：2010-03-03

Applicant: Yasushi Tamura ,  Ryouji Suezaki ,  Tetsuya Ohsawa ,  Hiroyuki Tanabe ,  Hitoki Kanagawa

Inventor： Yasushi Tamura ,  Ryouji Suezaki ,  Tetsuya Ohsawa ,  Hiroyuki Tanabe ,  Hitoki Kanagawa

IPC: H05K1/00

CPC classification number: G03F7/2022 ,  G03F1/144 ,  G03F1/70 ,  G11B5/4846 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/28 ,  H05K2201/0191 ,  H05K2203/0505 ,  H05K2203/0588 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A suspension board with circuit includes a metal supporting board, an insulating base layer formed on the metal supporting board, a conductive pattern formed on the insulating base layer, an insulating cover layer formed on the insulating base layer so as to cover the conductive pattern, and an insertion portion to be inserted into an E-block. A thickness of the insulating cover layer in the insertion portion is larger than a thickness of the insulating cover layer in a portion other than the insertion portion.

Abstract translation: 具有电路的悬挂板包括金属支撑板，形成在金属支撑板上的绝缘基底层，形成在绝缘基底层上的导电图案，形成在绝缘基底层上以覆盖导电图案的绝缘覆盖层， 以及插入到E块中的插入部。 插入部中的绝缘覆盖层的厚度比除了插入部以外的部分的绝缘覆盖层的厚度大。

公开(公告)号：US08418254B2

公开(公告)日：2013-04-09

申请号：US11490616

申请日：2006-07-21

Applicant: Michael A. Britti ,  Robert D. Thornley ,  Joel R. Springer ,  Michael J. Mauseth ,  Michael J. Collins

Inventor： Michael A. Britti ,  Robert D. Thornley ,  Joel R. Springer ,  Michael J. Mauseth ,  Michael J. Collins

IPC: G06F17/30

CPC classification number: H01L23/49822 ,  G06F21/62 ,  G06Q10/06 ,  G06Q10/0635 ,  G06Q10/10 ,  G06Q10/1053 ,  G06Q20/3674 ,  G06Q40/02 ,  G06Q40/025 ,  G06Q50/16 ,  G06Q50/20 ,  H01L21/48 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0271 ,  H05K3/4682 ,  H05K2201/0191 ,  H05K2201/0209

Abstract: Systems and methods for screening applicants are disclosed herein. A method of screening applicants is performed by a screening server. The server begins by receiving a selection of screening services and an applicant profile that identifies an applicant. The screening continues by generating screening results specified by the selection of screening services based on the applicant profile. A property manager is then notified that the screening results are available for the applicant based upon the applicant profile. The screening results are then provided to the property manager based upon the applicant profile. Based on these screening results, the screener or porperty manager can make a decision about the applicant and communicate a decision action to the applicant.

Abstract translation: 本文公开了筛选申请人的系统和方法。 筛选申请人的方法由筛选服务器执行。 服务器首先接收筛选服务的选择以及识别申请人的申请人简介。 根据申请人的资料，通过筛选服务选择筛选结果进行筛选。 然后通知物业经理，根据申请人的资料，可以为申请人提供筛选结果。 然后根据申请人的资料将筛选结果提供给物业经理。 根据这些筛选结果，筛选人员或经营者可以对申请人作出决定，并向申请人传达决定权。

公开(公告)号：US20120175151A1

公开(公告)日：2012-07-12

申请号：US13325815

申请日：2011-12-14

Applicant: Masaki MIZUTANI

Inventor： Masaki MIZUTANI

IPC: H05K1/02 ,  H05K3/36

CPC classification number: G11B5/4853 ,  G11B5/484 ,  G11B5/486 ,  H05K1/056 ,  H05K1/189 ,  H05K2201/0191 ,  H05K2201/09081 ,  Y10T29/49126

Abstract: A suspension board with circuit includes a gimbal portion. The gimbal portion includes a tongue portion formed at the inner side of the opening for being mounted with a slider mounted with a magnetic head for being electrically connected to the conductive layer, an outrigger portion formed at the outer side of the opening to support the tongue portion, and a passing portion passing through the opening of the gimbal portion and/or an outer side region of the outrigger portion. The passing portion includes the conductive layer and the insulating layer covering the conductive layer. The thickness of a lower half portion of the insulating layer in the passing portion is the same as that of an upper half portion thereof.

Abstract translation: 具有电路的悬挂板包括万向节部分。 万向节部分包括在开口的内侧形成的舌部，用于安装有安装有用于电连接到导电层的磁头的滑块，形成在开口的外侧以支撑舌头的外伸支架部分 并且穿过通过万向架部分的开口和/或外伸支架部分的外侧区域的通过部分。 通过部分包括导电层和覆盖导电层的绝缘层。 通过部分中的绝缘层的下半部分的厚度与其上半部分的厚度相同。

公开(公告)号：US20120146748A1

公开(公告)日：2012-06-14

申请号：US13400965

申请日：2012-02-21

Applicant: Mohammad Tabatabai

Inventor： Mohammad Tabatabai

IPC: H01P3/08

CPC classification number: H01P3/026 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09318

Abstract: According to one exemplary embodiment, a circuit board for reducing dielectric loss, conductor loss, and insertion loss includes a pair of transmission lines. The pair of transmission lines has sufficient thickness to cause substantial broadside electromagnetic coupling between the pair of transmission lines, where the pair of transmission lines is sufficiently separated from a ground plane of the circuit board so as to cause negligible electromagnetic coupling to the ground plane relative to the substantial broadside electromagnetic coupling. The pair of transmission lines thereby reduce dielectric loss, conductor loss, and insertion loss for signals traversing through the transmission line pair. The pair of transmission lines can be separated from the ground plane by, for example, at least 50.0 mils.

Abstract translation: 根据一个示例性实施例，用于降低介质损耗，导体损耗和插入损耗的电路板包括一对传输线。 这对传输线具有足够的厚度，以在一对传输线之间产生实质的宽边电磁耦合，其中一对传输线与电路板的接地平面充分分离，从而使接地平面的电磁耦合可以忽略不计 到实质的宽边电磁耦合。 这对传输线因此减少了穿过传输线对的信号的介质损耗，导体损耗和插入损耗。 这对传输线可以通过例如至少50.0密耳从地平面分离。

公开(公告)号：US08093712B2

公开(公告)日：2012-01-10

申请号：US13094105

申请日：2011-04-26

Applicant: Joseph C. Fjelstad

Inventor： Joseph C. Fjelstad

IPC: H01L21/00

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2924/19105 ,  H05K1/0278 ,  H05K3/1241 ,  H05K2201/0191 ,  H05K2201/09118 ,  H05K2203/1469

Abstract: A method (10) for manufacturing a monolithic molded electronic assembly (12). A mold (14) having first and second mold potions (14a-b) that mate to form an interior chamber (16) is provided. The mold has an injection port (22) and channel (24) connecting into the chamber. Electronic parts (30) having electronic contacts (32) are populated onto the second mold portion, to be substantially contained in the chamber. The mold potions are mated together and a liquid insulating molding material (36) is injected through the injection port channel to fill the chamber. The molding material is hardened to a solid, thereby embedding the electronic parts in the molding material as a monolithic sub-assembly (40). The monolithic sub-assembly is removed from the mold and one or more solderless conductive circuits (50) are applied to the electronic contacts of the electronic parts, thereby providing the electronic assembly.

Abstract translation: 一种用于制造单片模制电子组件（12）的方法（10）。 提供具有配合以形成内部腔室（16）的第一和第二模具部分（14a-b）的模具（14）。 模具具有连接到腔室中的注射口（22）和通道（24）。 具有电子触点（32）的电子部件（30）填充到第二模具部分上，以基本上容纳在腔室中。 将模具配合在一起，并且通过注入口通道注入液体绝缘模塑材料（36）以填充腔室。 将成型材料硬化成固体，从而将电子部件嵌入到成型材料中作为整体式子组件（40）。 将单片子组件从模具中取出，并且将一个或多个无焊导电电路（50）施加到电子部件的电子触点，从而提供电子组件。

公开(公告)号：US20110256363A1

公开(公告)日：2011-10-20

申请号：US13141988

申请日：2009-12-08

Applicant: Masataka Satou

Inventor： Masataka Satou

IPC: B32B3/10 ,  H05K3/06 ,  B32B15/04 ,  B32B5/00 ,  B05D5/12

CPC classification number: H05K3/387 ,  H05K3/064 ,  H05K3/067 ,  H05K2201/0191 ,  H05K2203/0709 ,  H05K2203/1361 ,  H05K2203/1366 ,  Y10T428/12451 ,  Y10T428/12472 ,  Y10T428/24917 ,  Y10T428/265 ,  Y10T428/31678

Abstract: A surface metal film material including, in this order, a substrate, a polymer layer that receives a plating catalyst or a precursor thereof, and a metal film formed by plating, wherein, when x μm represents surface roughness (Ra) at the interface between the substrate and the polymer layer, and y μm represents surface roughness (Ra) at the interface between the polymer layer and the metal film, x>y and 5 μm>x>0.1 μm, and wherein, when T μm represents a thickness of the polymer layer, T and x satisfy the relationship 2x≦T.

Abstract translation: 一种表面金属膜材料，其依次包括基板，接收电镀催化剂或其前体的聚合物层和通过电镀形成的金属膜，其中当x m表示在电镀之前的界面处的表面粗糙度（Ra） 基板和聚合物层，y m表示聚合物层和金属膜之间的界面处的表面粗糙度（Ra），x> y且5μm> x>0.1μm，并且其中，当Tμm表示 聚合物层T和x满足关系2x＆nlE; T。

公开(公告)号：US08015701B2

公开(公告)日：2011-09-13

申请号：US12035683

申请日：2008-02-22

Applicant: Paul V. Abrahamson ,  John Richard Dangler ,  Daniel Lee Dawiedczyk ,  Matthew Stephen Doyle

Inventor： Paul V. Abrahamson ,  John Richard Dangler ,  Daniel Lee Dawiedczyk ,  Matthew Stephen Doyle

IPC: H05K3/20

CPC classification number: H05K1/024 ,  H05K1/0393 ,  H05K3/386 ,  H05K3/4626 ,  H05K3/4635 ,  H05K3/4688 ,  H05K2201/015 ,  H05K2201/0191 ,  H05K2201/0715 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49163

Abstract: A flexible printed circuit assembly with a fluorocarbon dielectric layer and an adhesive layer with reduced thickness. The flexible printed circuit assembly includes a first dielectric layer and a signal trace disposed on the first dielectric layer. An adhesive layer with a thickness smaller than a height of the signal trace is disposed on the first dielectric layer, so that only a portion of a side surface of the signal trace is covered. A second dielectric layer made of fluorocarbon is disposed on the adhesive layer, covering a remaining portion of the side surface of the signal trace and a top surface of the signal trace.

Abstract translation: 一种柔性印刷电路组件，具有碳氟介电层和厚度减小的粘合剂层。 柔性印刷电路组件包括第一介电层和布置在第一介电层上的信号迹线。 厚度小于信号迹线的高度的粘合剂层设置在第一介电层上，使得仅覆盖信号迹线的侧表面的一部分。 由氟碳制成的第二电介质层设置在粘合剂层上，覆盖信号迹线的侧表面的剩余部分和信号迹线的顶表面。

公开(公告)号：US08003897B2

公开(公告)日：2011-08-23

申请号：US12713274

申请日：2010-02-26

Applicant: Yoichiro Kawamura ,  Shigeki Sawa ,  Katsuhiko Tanno ,  Hironori Tanaka ,  Naoaki Fujii

Inventor： Yoichiro Kawamura ,  Shigeki Sawa ,  Katsuhiko Tanno ,  Hironori Tanaka ,  Naoaki Fujii

IPC: H05K1/11

CPC classification number: H05K3/3478 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/3452 ,  H05K2201/0191 ,  H05K2201/099 ,  H05K2203/041 ,  H05K2203/0557 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. Connection reliability and insulation reliability are easily improved by making the ratio (H/D) of a height H from solder resist layer surface the solder bump to an opening diameter of the opening about 0.55 to about 1.0 even in narrow pitch structure under the pitch of the opening provided in the solder resist layer of about 200 μm or less.

Abstract translation: 一种印刷电路板，包括设置有至少一个导体电路的布线基板，形成在所述布线基板的表面上的阻焊层，覆盖所述至少一个导体电路，形成在所述至少一个导体电路的一部分上的导体焊盘 从设置在用于安装电子部件的阻焊层中的各个开口露出，以及形成在各个导体焊盘上的焊料凸块。 通过使窄阻抗层的高度H与焊锡凸块的比例（H / D）在开口直径大约0.55至1.0左右，在窄间距结构下，在距离 设置在阻焊层上的开口约为200μm以下。