公开(公告)号：US20140335659A1

公开(公告)日：2014-11-13

申请号：US14340665

申请日：2014-07-25

申请人： ROHM CO., LTD.

发明人： Toshio NAKASAKI

IPC分类号： H01L23/00 ,  H01L21/764 ,  H01L21/304 ,  H01L21/78

CPC分类号： H01L24/97 ,  H01L21/3043 ,  H01L21/6836 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/786 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/056 ,  H01L2224/06131 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2924/01019 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate.

摘要翻译： 半导体器件包括：第一半导体芯片，包括第一表面，第二表面和布置在第一表面上的第一端子;第二半导体芯片，包括第一表面，第二表面和第二端子，所述第二表面布置在第二表面的第二表面上 半导体芯片，包括结合到第一半导体芯片和第二半导体芯片的第二表面的第一表面的支撑基板，以及形成在支撑基板的第一表面上的隔离槽。 隔离包括分别从第一半导体芯片和第二半导体芯片的相对侧表面连续延伸的一对侧表面，并且隔离槽形成为支撑基板，以从支撑基板的第一表面延伸。 隔离槽的深度小于支撑基板的厚度。

公开(公告)号：US20130316471A1

公开(公告)日：2013-11-28

申请号：US13954641

申请日：2013-07-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

IPC分类号： H01L21/78 ,  H01L21/66

CPC分类号： H01L21/78 ,  H01L21/782 ,  H01L21/784 ,  H01L21/786 ,  H01L22/10 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.

摘要翻译： 半导体晶片结构包括多个模具，沿着第一方向延伸的第一划线，沿着第二方向延伸并且与第一划线交叉的第二划线，其中第一划线和第二划线具有交叉区域。 在划线中形成测试线，其中测试线穿过交叉区域。 测试垫形成在测试线中，并且仅在基本上在交叉区域中限定的自由区域的外部。

公开(公告)号：US20120091555A1

公开(公告)日：2012-04-19

申请号：US13275430

申请日：2011-10-18

申请人： Toshio NAKASAKI

发明人： Toshio NAKASAKI

IPC分类号： H01L27/00 ,  H01L21/76

CPC分类号： H01L24/97 ,  H01L21/3043 ,  H01L21/6836 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/786 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/056 ,  H01L2224/06131 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2924/01019 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate.

摘要翻译： 半导体器件包括：第一半导体芯片，包括第一表面，第二表面和布置在第一表面上的第一端子;第二半导体芯片，包括第一表面，第二表面和第二端子，所述第二表面布置在第二表面的第二表面上 半导体芯片，包括结合到第一半导体芯片和第二半导体芯片的第二表面的第一表面的支撑基板，以及形成在支撑基板的第一表面上的隔离槽。 隔离包括分别从第一半导体芯片和第二半导体芯片的相对侧表面连续延伸的一对侧表面，并且隔离槽形成为支撑基板，以从支撑基板的第一表面延伸。 隔离槽的深度小于支撑基板的厚度。

公开(公告)号：US20080073753A1

公开(公告)日：2008-03-27

申请号：US11525575

申请日：2006-09-22

申请人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

发明人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

IPC分类号： H01L23/544

CPC分类号： H01L21/78 ,  H01L21/782 ,  H01L21/784 ,  H01L21/786 ,  H01L22/10 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.

摘要翻译： 半导体晶片结构包括多个模具，沿着第一方向延伸的第一划线，沿着第二方向延伸并且与第一划线交叉的第二划线，其中第一划线和第二划线具有交叉区域。 在划线中形成测试线，其中测试线穿过交叉区域。 测试垫形成在测试线中，并且仅在基本上在交叉区域中限定的自由区域的外部。

公开(公告)号：US06613650B1

公开(公告)日：2003-09-02

申请号：US09569111

申请日：2000-05-10

申请人： Scott H. Holmberg

发明人： Scott H. Holmberg

IPC分类号： H01L2100

CPC分类号： G02F1/1309 ,  G02F1/136204 ,  H01L21/786 ,  H01L27/0248

摘要： An improved method of manufacturing active matrix displays with ESD protection through final assembly and in process testing and repair capabilities. At least a first set of shorting bars is formed adjacent the row and column matrix. The shorting bars are respectively coupled to one another in series to allow testing of the matrix elements. A first shorting bar is coupled to the row lines and a second shorting bar is coupled to the column lines. The shorting bars can remain coupled to the matrix through final assembly to provide ESD protection and final assembly and testing capability.

摘要翻译： 通过最终组装和过程测试和修复功能制造具有ESD保护功能的有源矩阵显示器的改进方法。 在行和列矩阵附近形成至少第一组短路棒。 短路棒分别彼此耦合以允许对矩阵元件的测试。 第一短路条耦合到行线，并且第二短路条耦合到列线。 短路棒可以通过最终组装保持与矩阵的耦合，以提供ESD保护和最终组装和测试能力。