公开(公告)号：US09817610B1

公开(公告)日：2017-11-14

申请号：US14963148

申请日：2015-12-08

Applicant: INPHI CORPORATION

Inventor： Aws Shallal ,  Dan Kunkel

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F11/14 ,  G06F12/0238 ,  G06F12/0804 ,  G06F12/0868 ,  G06F13/16 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/1056 ,  G06F2212/214 ,  G06F2212/313

Abstract: An apparatus forms a memory system that is physically populated into a host. In a powered-on state, the apparatus logically connects to the host through a host memory controller configured to receive host-initiated commands. The memory system includes a command buffer coupled to the host memory controller to receive the host-initiated commands. The memory system comprises both volatile memory (e.g., RAM) and non-volatile memory (e.g., FLASH). A non-volatile memory controller (NVC) is coupled to the volatile memory, and is also coupled to the non-volatile memory. A command sequence processor that is co-resident with the NVC responds to a trigger signal by logically disconnecting from the host, then dispatching command sequences that perform successive read/write operations between the volatile memory and the non-volatile memory. The successive read/write operations are performed even when the host is in a powered-down state.

公开(公告)号：US09804966B1

公开(公告)日：2017-10-31

申请号：US15083662

申请日：2016-03-29

Applicant: EMC CORPORATION

Inventor： Sandeep Sadanandan

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0877

CPC classification number: G06F12/0862 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/10 ,  G06F12/0868 ,  G06F12/0877 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/261 ,  G06F2212/312 ,  G06F2212/6024

Abstract: Methods and apparatus to determine priority information from read and/or write access of data blocks with addressing to physical storage based upon unique identifiers derived from content of data blocks. Time information for the respective data blocks can be stored. In embodiments, data blocks can be moved and/or copied based upon the priority information.

公开(公告)号：US09804922B2

公开(公告)日：2017-10-31

申请号：US14336883

申请日：2014-07-21

Applicant: SanDisk Technologies Inc.

Inventor： Mrinal Kochar ,  Abhijeet Bhalerao ,  Derek McAuley ,  Piyush Sagdeo

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G06F12/08 ,  G06F11/07 ,  G11C29/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20

CPC classification number: G06F11/1068 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/141 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2094 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C29/52 ,  G11C29/765

Abstract: Systems and methods for partial bad block reuse may be provided. Data may be copied from a block of a first memory to a block of a second memory. A post write read error may be detected in a first portion the data copied to the block of the second memory without detection of a post write read error in a second portion of the data copied to the block of the second memory. The block of the second memory may be determined to be a partial bad block usable for storage in response to detection of the post write read error in the first portion of the data but not in the second portion of the data.

公开(公告)号：US09798472B1

公开(公告)日：2017-10-24

申请号：US14868690

申请日：2015-09-29

Applicant: EMC Corporation

Inventor： Assaf Natanzon ,  Eitan Bachmat ,  Mark Abashkin

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/128

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/69 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: A System, Computer Program Product, and Computer-executable method for managing cache de-staging on a data storage system wherein the data storage system provides a Logical Unit (LU), the System, Computer Program Product, and Computer-executable method including dividing the LU into two or more extents, analyzing each of the two or more extents, creating a cache de-staging policy based on the analysis, and managing cache de-staging of the LU based the cache de-staging policy.

公开(公告)号：US20170293566A1

公开(公告)日：2017-10-12

申请号：US15508028

申请日：2014-09-09

Applicant: HUA ZHONG UNIVERSITY OF SCIENCE TECHNOLOGY

Inventor： Dan Feng ,  Wen Zhou ,  Jingning Liu ,  Wei Tong ,  Yu Hua ,  Shuangwu Zhang

IPC: G06F12/0888 ,  G06F12/0864

CPC classification number: G06F12/0888 ,  G06F12/0246 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/121 ,  G06F2212/1008 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/60 ,  G06F2212/7202

Abstract: Technologies are generally described herein to detect non-volatile write request sequences. A write request is received to write to a solid-state device that includes the non-volatile memory. A determination is made as to whether the write request is part of a non-volatile write request sequence or is not pan of the non-volatile write request sequence, in response to determining that the write request is part of the non-volatile write request sequence, the write request is associated with the non-volatile write request sequence. In response to determining that the write request is not part of the non-volatile write request sequence, the data associated with the write request is written to a cache that is coupled to the non-volatile memory. The data associated with the non-volatile write request sequences may be written directly to the non-volatile memory.

公开(公告)号：US20170293430A1

公开(公告)日：2017-10-12

申请号：US15270884

申请日：2016-09-20

Applicant: SK hynix Inc.

Inventor： Beom-Ju SHIN

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0679 ,  G06F11/1048 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/214 ,  G06F2212/403 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C29/52

Abstract: A data processing system may include: a first memory system including a first memory device, and a first controller of the first memory device; and a second memory system including a second memory device, and a second controller of the second memory device, the first memory system may receive a command from a host, and then checks time information included in the command and performs a first update operation for the first memory device for a first time corresponding to the time information, and the second memory system may perform a second update operation for the second memory device for the first time for which the first update operation is performed.

公开(公告)号：US09785365B1

公开(公告)日：2017-10-10

申请号：US14963098

申请日：2015-12-08

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Collins Williams ,  Dan Kunkel ,  William Wolf

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F11/14

CPC classification number: G06F11/1446 ,  G06F3/0608 ,  G06F11/1448 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0868 ,  G06F13/28 ,  G06F2212/1024 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/313

Abstract: The present invention is directed to memory systems. More specifically, embodiments of the present invention provide a memory system with a volatile memory, a persistent memory, and a controller. In a save operation, the controller copies contents of the volatile memory to the persistent memory as data units with their corresponding descriptor fields, where the descriptor fields include address information. In a restore operation, the controller copies data units from the persistent memory to their corresponding locations based on addresses stored at descriptor fields. There are other embodiments as well.

公开(公告)号：US20170286307A1

公开(公告)日：2017-10-05

申请号：US15085485

申请日：2016-03-30

Applicant: Infinio Systems, Inc.

Inventor： David W. Harvey ,  Scott H. Davis ,  Martin Charles Martin ,  Vishal Misra ,  Hooman Vassef

IPC: G06F12/08

CPC classification number: G06F12/0866 ,  G06F11/1446 ,  G06F12/0864 ,  G06F12/1018 ,  G06F2212/1004 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/222 ,  G06F2212/281 ,  G06F2212/461 ,  G06F2212/466

Abstract: Systems and methods for a content addressable cache that is optimized for SSD use are disclosed. In some embodiments, the cache utilizes an identifier array where identification information is stored for each entry in the cache. However, the size of the bit field used for the identification information is not sufficient to uniquely identify the data stored at the associated entry in the cache. A smaller bit field increases the likelihood of a “false positive”, where the identification information indicates a cache hit when the actual data does not match the digest. A larger bit field decreases the probability of a “false positive”, at the expense of increased metadata memory space. Thus, the architecture allows for a compromise between metadata memory size and processing cycles.

公开(公告)号：US09778846B2

公开(公告)日：2017-10-03

申请号：US15244163

申请日：2016-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G06F12/14 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/14 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/214 ,  G06F2212/2532 ,  Y02D10/14

Abstract: Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

公开(公告)号：US09767041B2

公开(公告)日：2017-09-19

申请号：US14721625

申请日：2015-05-26

Applicant: Intel Corporation

Inventor： Aravindh V. Anantaraman ,  Zvika Greenfield ,  Israel Diamand ,  Anant V. Nori ,  Pradeep Ramachandran ,  Nir Misgav

IPC: G06F12/12 ,  G06F12/08 ,  G06F12/121 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0893 ,  G06F12/0864 ,  G06F12/123 ,  G06F12/128 ,  G06F9/44

CPC classification number: G06F12/121 ,  G06F9/4418 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/608

Abstract: Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in the cache memory, perform a lookup operation for the first data element in the volatile memory and in response to a failed lookup operation, to generate a cache scrub hint forward the cache scrub hint to a cache scrub engine and identify one or more cache lines to scrub based at least in part on the cache scrub hint. Other examples are also disclosed and claimed.