公开(公告)号：US5835790A

公开(公告)日：1998-11-10

申请号：US526278

申请日：1995-09-11

Applicant: Eiichi Nagai ,  Yoshihiro Takemae ,  Hirohiko Mochizuki ,  Yukihiro Nomura

Inventor： Eiichi Nagai ,  Yoshihiro Takemae ,  Hirohiko Mochizuki ,  Yukihiro Nomura

IPC: G06F9/38 ,  G06F12/00 ,  G11C7/10 ,  G06F3/00

CPC classification number: G11C7/1051 ,  G06F9/3869 ,  G11C7/1039

Abstract: A data transfer apparatus is disclosed which has a first, a second, and a third pipeline processing circuits disposed in cascade connection. The first and the second pipeline processing circuits are each provided with an arbitrary signal processing circuit, a switch element for controlling the introduction of data into the signal processing circuit, and a switch control circuit for turning on the switch element on detecting completion of the transfer of data from the signal processing circuit to a pipeline processing circuit in the subsequent stage. The third pipeline processing circuit is provided with an output circuit and a switch element for introducing data transferred from the second pipeline processing circuit into the output circuit as synchronized with an external clock signal. Between the first and the second pipeline processing circuit, therefore, data can be transferred with a timing conforming to the timing of the operation of the signal processing circuit without being synchronized with an external clock signal. In the output circuit, data can be issued as synchronized with an external clock signal. Thus, a signal of a very high frequency can be selected as a clock signal for setting the timing of the whole of a system incorporating the data transfer apparatus therein.

Abstract translation: 公开了一种数据传送装置，其具有级联连接设置的第一，第二和第三流水线处理电路。 第一和第二流水线处理电路分别设置有任意的信号处理电路，用于控制将数据引入信号处理电路的开关元件，以及用于在检测到转印完成时接通开关元件的开关控制电路 的数据从信号处理电路到后续阶段的流水线处理电路。 第三流水线处理电路设置有与外部时钟信号同步地将从第二流水线处理电路传送的数据引入输出电路的输出电路和开关元件。 因此，在第一和第二流水线处理电路之间，可以以与外部时钟信号同步的信号处理电路的操作的定时的定时来传送数据。 在输出电路中，数据可以与外部时钟信号同步发出。 因此，可以选择非常高频率的信号作为用于设置其中包含数据传送装置的系统整体的定时的时钟信号。

公开(公告)号：US5483497A

公开(公告)日：1996-01-09

申请号：US277486

申请日：1994-07-19

Applicant: Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Katsumi Shigenobu

Inventor： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Yukinori Kodama ,  Makoto Yanagisawa ,  Katsumi Shigenobu

IPC: G11C11/41 ,  G06F12/06 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C7/00

CPC classification number: G06F12/0623 ,  G11C8/12

Abstract: A semiconductor memory having a plurality of banks, a first specify unit, and a second specify unit. The first specify unit is used to specify one of the banks by decoding a bank address signal contained in a row address signal. The second specify unit is used to specify one of the banks by decoding the bank address signal contained in the row address signal, according to bank status signals that indicate whether or not each of the banks is activated. Therefore, the semiconductor memory is used for different bank configurations. Namely, with this arrangement, the semiconductor memory is capable of serving as a memory having a smaller number of banks, to thereby improve convenience.

Abstract translation: 具有多个存储体的半导体存储器，第一指定单元和第二指定单元。 第一指定单元用于通过解码包含在行地址信号中的存储体地址信号来指定存储体之一。 第二指定单元用于根据指示每个存储体是否被激活的存储体状态信号对包含在行地址信号中的存储体地址信号进行解码来指定存储区之一。 因此，半导体存储器用于不同的存储体配置。 也就是说，通过这种布置，半导体存储器能够用作具有较少数量的存储体的存储器，从而提高方便性。

公开(公告)号：US4766573A

公开(公告)日：1988-08-23

申请号：US26519

申请日：1987-03-17

Applicant: Yoshihiro Takemae

Inventor： Yoshihiro Takemae

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/401 ,  G11C11/406 ,  G11C29/42 ,  G11C7/00 ,  G06F11/00

CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C11/406

Abstract: A semiconductor memory includes a plurality of cell blocks, a refresh control circuit which sequentially refreshes a plurality of the cell blocks, an access control circuit which accesses a plurality of the cell blocks, and an ECC circuit which is provided in a data path between the access control circuit and the plurality of cell blocks, so that the data which is input from and output to the access control circuit is converted to a predetermined bit converted data (so called code) by the ECC circuit and is stored in the plurality of cell blocks. Accordingly, when the access control circuit accesses the plurality of cell blocks, if the access cannot be carried out for specified cell block which is in a refresh state (that is, a correct data (code) cannot be written to or read from the cell block in a refresh state) the data in the access control circuit side can be reproduced as correct data by the ECC circuit. Therefore, viewed from the external, a predetermined access can be carried out without being affected by the refresh state.

Abstract translation: 半导体存储器包括多个单元块，顺序地刷新多个单元块的刷新控制电路，访问多个单元块的访问控制电路，以及设置在第二单元块之间的数据通路中的ECC电路 访问控制电路和多个单元块，使得从ECC电路将输入和输出到访问控制电路的数据转换为预定位转换数据（所谓代码），并存储在多个单元中 块。 因此，当访问控制电路访问多个单元块时，如果对于处于刷新状态的指定单元块（即，正确的数据（代码）不能被写入或从单元读取），则不能执行访问 块处于刷新状态），访问控制电路侧的数据可以由ECC电路作为正确的数据再现。 因此，从外部观察，可以执行预定的访问而不受刷新状态的影响。

公开(公告)号：US4758993A

公开(公告)日：1988-07-19

申请号：US798785

申请日：1985-11-18

Applicant: Yoshihiro Takemae

Inventor： Yoshihiro Takemae

IPC: G11C7/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/406 ,  G11C11/408 ,  G11C8/00

CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/408 ,  G11C7/1045 ,  G11C8/12 ,  G11C8/14

Abstract: A dynamic random access memory (DRAM) device is formed on a semiconductor substrate, the device having an array of memory cells which are divided in several sub-arrays. The device has memory blocks each containing one of the sub-arrays, a word decoder and column decoder. Each of the memory blocks is selected independently to perform an access operation and refresh operation. As long as different memory blocks are selected for the respective operations, both operations are performed in parallel, however, when the same memory block is selected for both operations, namely, double selection, a comparison circuit detects the double selection and gives priority to one of the operations. The operation selected thus, preferentially performed. Usually, the refresh operations is then performed. However, in order to decrease the "busy ratio" of the device, the access operation is performed preferentially. Further, a complicated operation for priority selection may be performed according to a predetermined schedule memorized in a priority providing means. In addition, a common word bus line is proposed for accessing each of the memory blocks, namely, each sub-arrays, in order to reduce the number of common word lines for realizing a further high packing denisty of the DRAM device. This common bus line is also applicable to other devices such as a static RAM.

Abstract translation: 在半导体衬底上形成动态随机存取存储器（DRAM）器件，该器件具有分成多个子阵列的存储器单元阵列。 该设备具有每个包含子阵列之一，字解码器和列解码器的存储器块。 每个存储块被独立地选择以执行访问操作和刷新操作。 只要为相应的操作选择不同的存储器块，则两个操作并行执行，然而，当为两个操作（即双重选择）选择相同的存储器块时，比较电路检测双重选择并优先考虑一个 的操作。 因此优先执行所选择的操作。 通常，执行刷新操作。 然而，为了降低设备的“忙比”，优先进行访问操作。 此外，可以根据存储在优先级提供装置中的预定时间表执行用于优先级选择的复杂操作。 此外，为了减少用于实现DRAM器件的进一步高封装否定的通用字线的数量，提出了用于访问每个存储器块即每个子阵列的公共字总线。 该公共总线也适用于其他设备，如静态RAM。

公开(公告)号：US4752914A

公开(公告)日：1988-06-21

申请号：US739159

申请日：1985-05-30

Applicant: Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Kimiaki Sato ,  Norihisa Tsuge ,  Itaru Tsuge ,  Sachie Tsuge

Inventor： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Kimiaki Sato ,  Norihisa Tsuge ,  Itaru Tsuge ,  Sachie Tsuge

IPC: G11C29/00 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C29/835

Abstract: A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.

Abstract translation: 一种半导体集成电路，包括存储单元，用于存储故障电路部分的地址信息，并通过冗余电路部分来替换故障电路部分。 半导体集成电路提供用于检测从存储单元读取的数据与接收到的输入地址之间的一致性的比较单元。 通过比较单元的比较产生的数据通过外部连接终端传送。

公开(公告)号：US4745577A

公开(公告)日：1988-05-17

申请号：US798284

申请日：1985-11-15

Applicant: Junji Ogawa ,  Yoshihiro Takemae

Inventor： Junji Ogawa ,  Yoshihiro Takemae

IPC: H01L27/08 ,  G11C7/10 ,  G11C19/00 ,  G11C7/00

CPC classification number: G11C7/1075

Abstract: A semiconductor memory device with shift registers used for a video RAM, including a memory cell array, bit lines, and word lines, a pair of shift registers, and transfer gate circuits arranged between the bit lines and the shift registers. Each parallel data transfer circuit is provided between the shift registers for transferring parallel data between the shift registers, so that high-speed reading and writing of data for a CRT display is realized.

Abstract translation: 具有用于视频RAM的移位寄存器的半导体存储器件，包括存储单元阵列，位线和字线，一对移位寄存器和布置在位线和移位寄存器之间的传输门电路。 每个并行数据传输电路设置在用于在移位寄存器之间传送并行数据的移位寄存器之间，从而实现用于CRT显示器的数据的高速读取和写入。

公开(公告)号：US4707806A

公开(公告)日：1987-11-17

申请号：US712149

申请日：1985-03-15

Applicant: Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

Inventor： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

IPC: H01L27/00 ,  G11C8/10 ,  G11C17/14 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H01L23/525 ,  G11C11/00

CPC classification number: G11C29/785 ,  G11C17/16 ,  G11C8/10 ,  H01L23/5256 ,  H01L2924/0002

Abstract: A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse.In a normal operation, the voltage output from the voltage level conversion circuit can be set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse to which the voltage is applied, but higher than the threshold voltage of the information detection circuit.

Abstract translation: 连接在第一和第二电压馈送线之间的装置包括信息存储电路，该信息存储电路具有熔丝，用于通过吹送或不熔断熔丝来存储信息;电压电平转换电路，连接到第一和第二电压馈送线中的至少一个并输出一个 电压低于第一和第二电压馈送线之间的电压到信息存储电路，以及电路，连接在第一和第二电压馈送线之间，用于响应于信息存储中的熔丝处的电压值输出检测信号 从电压电平转换电路向其施加电压的电路，以及哪个电压值随着保险丝的熔断或非吹出状态而变化。 在正常操作中，可以将从电压电平转换电路输出的电压设置得尽可能低以抑制在施加电压的熔丝的熔断部分附近引起的电迁移，但是高于 信息检测电路。

公开(公告)号：US4692689A

公开(公告)日：1987-09-08

申请号：US15529

申请日：1987-02-12

Applicant: Yoshihiro Takemae

Inventor： Yoshihiro Takemae

IPC: H03K19/00 ,  G05F1/56 ,  G05F3/24 ,  G11C11/407 ,  H03H11/24

CPC classification number: G05F3/242 ,  H03H11/245

Abstract: A voltage converting circuit has an output MIS transistor which gives a low output impedance and outputs an intermediate level of power source voltage. The output level is set with a high accuracy through a voltage dividing ratio determined by an impedance element. This impedance element is connected with a compensating MIS transistor to compensate for variations of the gate threshold voltage caused by the manufacturing process.

Abstract translation: 电压转换电路具有输出MIS晶体管，其输出低输出阻抗并输出中间电平的电源电压。 通过由阻抗元件确定的分压比，以高精度设置输出电平。 该阻抗元件与补偿MIS晶体管连接，以补偿由制造过程引起的栅极阈值电压的变化。

公开(公告)号：US4688219A

公开(公告)日：1987-08-18

申请号：US765817

申请日：1985-08-15

Applicant: Yoshihiro Takemae

Inventor： Yoshihiro Takemae

IPC: G11C11/34 ,  G06F11/10 ,  G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G11C29/42 ,  G06F11/00 ,  G11C7/00 ,  H03M13/00

CPC classification number: G11C29/70 ,  G06F11/1008 ,  G06F11/1076

Abstract: A semiconductor memory device which has an error correcting circuit and employs a virtual two-dimensional matrix for correcting read data is provided. The device includes a redundant memory cell to replace a defective memory cell. When the selected memory cell has a previously determined hard error, the selected memory cell is replaced by the redundant memory cell. When the selected memory cell has a soft error or a hard error occuring after the determination of the previously determined hard error, the read data is corrected by the error correcting circuit.

Abstract translation: 提供一种具有误差校正电路并采用虚拟二维矩阵来校正读取数据的半导体存储器件。 该装置包括用于替换有缺陷的存储单元的冗余存储单元。 当所选择的存储单元具有预先确定的硬错误时，所选存储单元被冗余存储单元替代。 当所选存储单元在确定先前确定的硬错误之后发生软错误或硬错误时，由纠错电路校正读取的数据。

公开(公告)号：US4680734A

公开(公告)日：1987-07-14

申请号：US762531

申请日：1985-08-05

Applicant: Fumio Baba ,  Yoshihiro Takemae

Inventor： Fumio Baba ,  Yoshihiro Takemae

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/20 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C7/00 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/20

Abstract: A semiconductor memory device having a data inverting circuit for selectively inverting an input/outpt data of a sense amplifier in such a way that the charging states of respective memory cells connected to two bit lines in each bit line pair become equal for the same input/output data. A clamp circuit draws the potentials of all of the bit lines to a predetermined potential in response to a clear control signal, whereby the contents of all of the memory cells are cleared at the same time.

Abstract translation: 一种半导体存储器件，具有数据反相电路，用于选择性地反相读出放大器的输入/输出数据，使得连接到每个位线对中的两个位线的各个存储单元的充电状态对于相同的输入/ 输出数据。 钳位电路响应于清除的控制信号将所有位线的电位拉到预定电位，从而同时清除所有存储单元的内容。