公开(公告)号：US11714717B2

公开(公告)日：2023-08-01

申请号：US17703857

申请日：2022-03-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Chia-Fu Lee ,  Chien-Yin Liu ,  Yi-Chun Shih ,  Kuan-Chun Chen ,  Hsueh-Chih Yang ,  Shih-Lien Linus Lu

IPC: G06F11/10 ,  H03M13/29 ,  H03M13/15 ,  H03M13/19 ,  G11C29/42

CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F11/1048 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2927 ,  G11C29/42 ,  H03M13/152 ,  H03M13/1515 ,  H03M13/19

Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.

公开(公告)号：US11688436B2

公开(公告)日：2023-06-27

申请号：US17829333

申请日：2022-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C7/062 ,  G11C7/08 ,  G11C7/12

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

公开(公告)号：US11651826B2

公开(公告)日：2023-05-16

申请号：US17693908

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C17/08 ,  G11C7/06 ,  G11C7/10 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C7/06 ,  G11C7/1063 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/26 ,  G11C17/08

Abstract: A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.

公开(公告)号：US20230121502A1

公开(公告)日：2023-04-20

申请号：US18064098

申请日：2022-12-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Lien Linus Lu ,  Kun-hsi Li ,  Shih-Liang Wang ,  Jonathan Tsung-Yung Chang ,  Yu-Der Chih ,  Cheng-En Lee

IPC: H04L9/08 ,  G06F7/58 ,  H04L9/32

Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.

公开(公告)号：US11621040B2

公开(公告)日：2023-04-04

申请号：US17365732

申请日：2021-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Meng-Fan Chang ,  May-Be Chen ,  Cheng-Xin Xue ,  Je-Syu Liu

IPC: G11C8/00 ,  G11C13/00 ,  G11C7/10 ,  G06F7/544 ,  G11C7/06

Abstract: A system includes a global generator and local generators. The global generator is coupled to a memory array, and is configured to generate global signals, according to a number of a computational output of the memory array. The local generators are coupled to the global generator and the memory array, and are configured to generate local signals, according to the global signals. Each one of the local generators includes a first reference circuit and a local current mirror. The first reference circuit is coupled to the global generator, and is configured to generate a first reference signal at a node, in response to a first global signal of the global signals. The local current mirror is coupled to the first reference circuit at the node, and is configured to generate the local signals, by mirroring a summation of at least one signal at the node.

公开(公告)号：US11450395B2

公开(公告)日：2022-09-20

申请号：US17237688

申请日：2021-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Gu-Huan Li ,  Chen-Ming Hung ,  Yu-Der Chih

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16 ,  G11C8/10 ,  G11C7/10

Abstract: A memory circuit includes a first bank of non-volatile memory (NVM) devices, a first plurality of decoders, a first plurality of high-voltage (HV) drivers corresponding to the first plurality of decoders, and a first plurality of HV power switches. A first HV power switch is coupled to each HV driver of the first plurality of HV drivers, and each decoder is configured to generate an enable signal corresponding to a column of the first bank of NVM devices. Each HV driver is configured to output a HV activation signal to the corresponding column of the first bank of NVM devices responsive to a power signal of the first HV power switch and to the enable signal of the corresponding decoder.

公开(公告)号：US11380371B2

公开(公告)日：2022-07-05

申请号：US17096966

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12

Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.

公开(公告)号：US20220165334A1

公开(公告)日：2022-05-26

申请号：US17105483

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih

IPC: G11C13/00

Abstract: The disclosure is directed to a memory circuit, an electronic device, and a method for implementing a ternary weight for in-memory computing. According to an aspect of the disclosure, the memory circuit includes a first memory cell having a first resistor; a second memory cell having a second resistor, a write driver configured to set the first resistor to a first resistance value, a second write driver configured to set the second resistor to a second resistance value, a differential current sensing circuit configured to determine a differential current between the first memory cell and the second memory cell based on the first resistance value and the second resistance value, and a ternary weight detector configured to determine a ternary weight which is selected among a first ternary weight, a second ternary weight, and a third ternary weight based on the differential current.

公开(公告)号：US20210350836A1

公开(公告)日：2021-11-11

申请号：US16870220

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C29/42 ,  G11C11/16

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

公开(公告)号：US20250021120A9

公开(公告)日：2025-01-16

申请号：US17877115

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Jun Lin ,  Chung-Cheng Chou ,  Yu-Der Chih ,  Chin-I Su

IPC: G05F1/575 ,  G05F1/565

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.