公开(公告)号：US10672665B2

公开(公告)日：2020-06-02

申请号：US16251642

申请日：2019-01-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shang-Wen Chang ,  Yi-Hsiung Lin ,  Yi-Hsun Chiu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/768

Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.

公开(公告)号：US20200098631A1

公开(公告)日：2020-03-26

申请号：US16531232

申请日：2019-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L21/768 ,  G06F17/50

Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.

公开(公告)号：US10096597B1

公开(公告)日：2018-10-09

申请号：US15626204

申请日：2017-06-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Chung-Cheng Wu ,  Guo-Yung Chen ,  Yi-Hsiung Lin ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a gate structure including a gate dielectric layer and a first gate electrode layer, and a second gate electrode layer. In the method for fabricating the semiconductor device, at first, the semiconductor substrate is provided. The semiconductor substrate includes fin portions. Then, a gate dielectric layer is formed on the fin portions. Thereafter, a first gate electrode layer is formed on the gate dielectric layer. Then, the first gate electrode layer is etched. Thereafter, a second electrode layer is formed on the first gate electrode layer. Therefore, the gate electrode layer formed on the gate dielectric layer is regrown with easy control.

公开(公告)号：US20240096805A1

公开(公告)日：2024-03-21

申请号：US18526445

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L24/05 ,  H01L24/13 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13026

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US20240088141A1

公开(公告)日：2024-03-14

申请号：US18511533

申请日：2023-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/50 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/50 ,  H01L27/0207

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

公开(公告)号：US11862561B2

公开(公告)日：2024-01-02

申请号：US17126509

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L24/05 ,  H01L24/13 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13026

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US11848327B2

公开(公告)日：2023-12-19

申请号：US17373255

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/50

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/50 ,  H01L27/0207

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

公开(公告)号：US20230013764A1

公开(公告)日：2023-01-19

申请号：US17683944

申请日：2022-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Yi-Hsun Chiu ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Min Cao

IPC: H01L23/522 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L23/528

Abstract: Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.

公开(公告)号：US11532556B2

公开(公告)日：2022-12-20

申请号：US16947390

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Cheng-Ting Chung ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate.

公开(公告)号：US20220328363A1

公开(公告)日：2022-10-13

申请号：US17358985

申请日：2021-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Yi-Hsun Chiu ,  Shang-Wen Chang ,  Ching-Wei Tsai ,  Chih-Hao Wang

IPC: H01L21/66 ,  H01L29/06 ,  H01L29/78 ,  H01L23/50 ,  H01L21/768

Abstract: Methods of forming dual-side super power rails in semiconductor devices, semiconductor devices including the same, and methods of testing the semiconductor devices are disclosed. In an embodiment, a device includes a transistor structure; a front-side interconnect structure on a front side of the transistor structure; and a back-side interconnect structure on a back side of the transistor structure. The front-side interconnect structure includes a front-side power delivery network (PDN) and a front-side input/output (I/O) pin. The back-side interconnect structure includes a back-side PDN.