公开(公告)号：US20060181323A1

公开(公告)日：2006-08-17

申请号：US10906343

申请日：2005-02-15

申请人： Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

发明人： Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00032

摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

摘要翻译： 在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。 通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。 将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压 在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

公开(公告)号：US20060101362A1

公开(公告)日：2006-05-11

申请号：US10904397

申请日：2004-11-08

申请人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

发明人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

公开(公告)号：US20050125760A1

公开(公告)日：2005-06-09

申请号：US10729750

申请日：2003-12-04

申请人： Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Clarence Ogilvie ,  Sebastian Ventrone

IPC分类号： G06F15/177 ,  G06F15/78 ,  G06F17/50 ,  H01L25/00 ,  H03K19/177

CPC分类号： G06F17/5054 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.

摘要翻译： 包括用于缓解瓶颈的FPGA（现场可编程门阵列）的结构以及用于操作该结构的方法。 FPGA包括多个FPGA元件，每个FPGA元件包括CLB（可配置逻辑块），指令队列和数据缓冲器。 可以通过第一本地IO（输入/输出）电路在FPGA中形成一个功能块（彼此分开）并移动到第二个本地IO电路。 在每个功能块内，映射的逻辑位置函数计算从存储在映射位置寄存器中的功能块的当前位置以及存储在映射的目的地寄存器中的目的地的步长的方向，距离和时间，以及时间 允许移动，并将步进的方向和距离存储在映射运动寄存器中。 然后，功能块根据存储在映射运动寄存器中的方向和距离移动。

公开(公告)号：US20050071575A1

公开(公告)日：2005-03-31

申请号：US10605366

申请日：2003-09-25

申请人： Kenneth Goodnow ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Francis Kampf ,  Jason Norman ,  Sebastian Ventrone

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0284

摘要： A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

摘要翻译： 一种半导体器件上传输数据的结构和相关方法，包括：半导体器件内的多个系统。 每个系统包括至少一个处理设备和本地存储器结构。 每个处理设备电耦合到每个系统内的每个本地存储器结构。 每个本地存储器结构电耦合到每个其他所述本地存储器结构。 每个本地存储器结构适于与每个处理设备共享地址空间。 每个处理设备适于将数据和指令传送到每个本地存储器结构。

公开(公告)号：US20050041448A1

公开(公告)日：2005-02-24

申请号：US10604328

申请日：2003-07-11

申请人： Rafael Blanco ,  John Cohn ,  Kenneth Goodnow ,  Douglas Stout ,  Sebastian Ventrone

发明人： Rafael Blanco ,  John Cohn ,  Kenneth Goodnow ,  Douglas Stout ,  Sebastian Ventrone

IPC分类号： G11C19/08 ,  H01L20060101

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y02D10/171

摘要： A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

摘要翻译： 一种在半导体器件上处理数据的结构和相关方法，包括形成在半导体器件上的输入岛，处理岛和输出岛。 输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。 处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。 输出岛适于由第二规定电压供电。 处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。 第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

公开(公告)号：US20050001280A1

公开(公告)日：2005-01-06

申请号：US10604205

申请日：2003-07-01

申请人： Robert Horton ,  David Milton ,  Clarence Ogilvie ,  Paul Schanely ,  Sebastian Ventrone

发明人： Robert Horton ,  David Milton ,  Clarence Ogilvie ,  Paul Schanely ,  Sebastian Ventrone

IPC分类号： G06F13/42 ,  H01L31/107 ,  H04L25/14

CPC分类号： G06F13/4247 ,  H04L25/14

摘要： The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line

摘要翻译： 本发明通过首先沿着分段数据线的第一段传播第一数据部分，然后沿着分段数据线的第二段传播第一数据部分并同时沿第二数据部分传播第二数据部分 分段数据线的第一段。 本发明将单个数据传输中断到这样的不同数据部分，并且随后将所有不同数据部分已经沿着分段数据线的所有部分单独发送，将不同的数据部分重新组合成单​​个数据传输

公开(公告)号：US20080024197A1

公开(公告)日：2008-01-31

申请号：US11846578

申请日：2007-08-29

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Keith Williams ,  Sebastian Ventrone

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Keith Williams ,  Sebastian Ventrone

IPC分类号： G05F1/10

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  H01L25/16 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19105 ,  Y02D10/171 ,  H01L2224/0401

摘要： A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.

摘要翻译： 一种降低低功率电子设备中的静态功耗的方法。 所述电子设备包括一个或多个功率岛，每个功率岛包括：将本地电网耦合到本地接地网的局部存储电容器; 以及连接在本地电网与本地接地网之间的功能电路; 将全球电网耦合到全球接地网的全球存储电容器，每个局部地电网连接到全球接地网; 一个或多个开关，每个开关选择性地将全局电网连接到单个和不同的对应的局部电网; 以及适于打开和关闭所述一个或多个开关的电力调度单元。

公开(公告)号：US20070242507A1

公开(公告)日：2007-10-18

申请号：US11279507

申请日：2006-04-12

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clearence Ogilvis ,  Sebastian Ventrone ,  Kelth Williams

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clearence Ogilvis ,  Sebastian Ventrone ,  Kelth Williams

IPC分类号： G11C11/34

CPC分类号： G11C11/417

摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

摘要翻译： 公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。 耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。 因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

公开(公告)号：US20070198808A1

公开(公告)日：2007-08-23

申请号：US11276236

申请日：2006-02-20

申请人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Sebastian Ventrone ,  Keith Williams

发明人： Kerry Bernstein ,  Kenneth Goodnow ,  Clarence Ogilvie ,  Christopher Reynolds ,  Sebastian Ventrone ,  Keith Williams

IPC分类号： G06F15/00

CPC分类号： G06F9/3869 ,  G11C27/026

摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

摘要翻译： 公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

公开(公告)号：US20070189076A1

公开(公告)日：2007-08-16

申请号：US11353493

申请日：2006-02-14

申请人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

发明人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

IPC分类号： G11C16/04

CPC分类号： G11C16/0466

摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory element that includes (1) one or more MOSFETs each including a dielectric material having a dielectric constant of about 3.9 to about 25; and (2) control logic coupled to at least one of the one or more MOSFETs. The control logic is adapted to (a) cause the memory element to operate in a first mode to store data; and (b) cause the memory element to operate in a second mode to change a threshold voltage of at least one of the one or more MOSFETs from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects data stored by the memory element when operated in the first mode. Numerous other aspects are provided.

摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储元件，其包括（1）一个或多个MOSFET，每个MOSFET包括具有约3.9至约25的介电常数的电介质材料; 和（2）耦合到所述一个或多个MOSFET中的至少一个的控制逻辑。 控制逻辑适于（a）使存储元件以第一模式操作以存储数据; 和（b）使存储元件在第二模式下操作以将一个或多个MOSFET中的至少一个的阈值电压从原始阈值电压改变到改变的阈值电压，使得改变的阈值电压影响由 存储元件在第一模式下操作。 提供了许多其他方面。