Semiconductor package
    41.
    发明授权

    公开(公告)号:US10607914B2

    公开(公告)日:2020-03-31

    申请号:US16110436

    申请日:2018-08-23

    Abstract: A semiconductor package includes a first semiconductor package including a core member having a through-hole, a first semiconductor chip disposed in the through-hole and having an active surface with a connection pad disposed thereon, a first encapsulant for encapsulating at least a portion of the first semiconductor chip, and a connection member disposed on the active surface of the first semiconductor chip and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, a second semiconductor package disposed on the first semiconductor package and including a wiring substrate electrically connected to the connection member, at least one second semiconductor chip disposed on the wiring substrate, and a second encapsulant for encapsulating at least a portion of the second semiconductor chip, and a heat dissipation member covering a lateral surface of the second semiconductor package and exposing an upper surface of the second encapsulant.

    Fan-out semiconductor package
    42.
    发明授权

    公开(公告)号:US10580759B2

    公开(公告)日:2020-03-03

    申请号:US16152237

    申请日:2018-10-04

    Abstract: A fan-out semiconductor package includes a first core member including a first through-hole, a first semiconductor chip disposed in the first through-hole of the first core member, a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip, a first connection member disposed on the first semiconductor chip and including a first redistribution layer, a second core member adhered to a lower surface of the first connection member and including a second through-hole, a second semiconductor chip disposed in the second through-hole of the second core member, a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member, a second connection member disposed on the second semiconductor chip and including a second redistribution layer, and a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer.

    Connection system of semiconductor packages using a printed circuit board

    公开(公告)号:US10535643B2

    公开(公告)日:2020-01-14

    申请号:US15973927

    申请日:2018-05-08

    Abstract: A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated circuit (PMIC).

    Fan-out semiconductor package for packaging semiconductor chip and capacitors

    公开(公告)号:US10373884B2

    公开(公告)日:2019-08-06

    申请号:US15278248

    申请日:2016-09-28

    Abstract: The fan-out semiconductor package includes: a semiconductor chip having an active surface having a connection pad disposed thereon and an inactive surface disposed to oppose the active surface; a first capacitor disposed adjacently to the semiconductor chip; an encapsulant at least partially encapsulating the first connection member and the semiconductor chip; a first connection member disposed on the encapsulant, the first capacitor, and the semiconductor chip, and a second capacitor disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed, wherein the first connection member includes a redistribution layer electrically connected to the connection pad of the semiconductor chip, the first capacitor, and the second capacitor, and the first capacitor and the second capacitor are electrically connected to the connection pad through a common power wiring of the redistribution layer.

    Case for electronic device
    47.
    外观设计

    公开(公告)号:USD1032588S1

    公开(公告)日:2024-06-25

    申请号:US29884364

    申请日:2023-02-10

    Designer: Han Kim

    Abstract: FIG. 1 is a front perspective view of a case for electronic device showing my new design;
    FIG. 2 is a front elevation view thereof;
    FIG. 3 is a rear elevation view thereof;
    FIG. 4 is a left side elevation view thereof;
    FIG. 5 is a right side elevation view thereof;
    FIG. 6 is a top plan view thereof;
    FIG. 7 is a bottom plan view thereof; and,
    FIG. 8 is a rear perspective view thereof.
    The broken lines in the figures illustrate portions of the case for electronic device that form no part of the claimed design.

    Case for electronic device
    50.
    外观设计

    公开(公告)号:USD986233S1

    公开(公告)日:2023-05-16

    申请号:US29771797

    申请日:2021-02-25

    Abstract: FIG. 1 is a front perspective view of a first embodiment of a case for electronic device, showing our new design;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a left-side view thereof;
    FIG. 5 is a right-side view thereof;
    FIG. 6 is a top view thereof;
    FIG. 7 is a bottom view thereof;
    FIG. 8 is a rear perspective view thereof;
    FIG. 9 is a front perspective view of a second embodiment of a case for electronic device, showing our new design;
    FIG. 10 is a front view thereof;
    FIG. 11 is a rear view thereof;
    FIG. 12 is a left-side view thereof;
    FIG. 13 is a right-side view thereof;
    FIG. 14 is a top view thereof;
    FIG. 15 is a bottom view thereof; and,
    FIG. 16 is a rear perspective view thereof.
    The broken lines in the drawings figures form no part of the claimed design and depict portions of the case for electronic device that form no part of the claimed design.

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