公开(公告)号：US10373884B2

公开(公告)日：2019-08-06

申请号：US15278248

申请日：2016-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han Kim ,  Mi Ja Han ,  Kang Heon Hur ,  Young Gwan Ko

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/498 ,  H01L23/64

Abstract: The fan-out semiconductor package includes: a semiconductor chip having an active surface having a connection pad disposed thereon and an inactive surface disposed to oppose the active surface; a first capacitor disposed adjacently to the semiconductor chip; an encapsulant at least partially encapsulating the first connection member and the semiconductor chip; a first connection member disposed on the encapsulant, the first capacitor, and the semiconductor chip, and a second capacitor disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed, wherein the first connection member includes a redistribution layer electrically connected to the connection pad of the semiconductor chip, the first capacitor, and the second capacitor, and the first capacitor and the second capacitor are electrically connected to the connection pad through a common power wiring of the redistribution layer.

公开(公告)号：US10714440B2

公开(公告)日：2020-07-14

申请号：US16042644

申请日：2018-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han Kim ,  Kyung Moon Jung ,  Seok Hwan Kim ,  Kyung Ho Lee ,  Kang Heon Hur

IPC: H01L23/00

Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

公开(公告)号：US10672719B2

公开(公告)日：2020-06-02

申请号：US15923708

申请日：2018-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang Heon Hur ,  Jong Man Kim ,  Kyung Ho Lee ,  Han Kim

IPC: H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L23/36

Abstract: A semiconductor package includes a wiring portion including an insulating layer, conductive patterns disposed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns, a semiconductor chip disposed on the wiring portion, an encapsulant disposed on the wiring portion and encapsulating at least a portion of the semiconductor chip, and a metal layer disposed on the semiconductor chip and the encapsulant and having a thickness of 10 μm to 70 μm.

公开(公告)号：US10403588B2

公开(公告)日：2019-09-03

申请号：US15402383

申请日：2017-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han Kim ,  Kyung Moon Jung ,  Seok Hwan Kim ,  Kyung Ho Lee ,  Kang Heon Hur

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/00

Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.