Fan-out sensor package
    1.
    发明授权

    公开(公告)号:US10998362B2

    公开(公告)日:2021-05-04

    申请号:US16915274

    申请日:2020-06-29

    Abstract: A fan-out sensor package includes: a substrate in which a through-hole is formed and portions of a wiring layer are exposed from an insulating layer; an image sensor having an active surface having a sensing region disposed below the through-hole of the substrate and connection pads disposed in the vicinity of the sensing region; an optical member disposed on the active surface of the image sensor; a dam member disposed in the vicinity of the sensing region; and an encapsulant encapsulating the substrate and the image sensor, wherein the third wiring layer and the connection pads are electrically connected to each other by connection members.

    Fan-out semiconductor package
    2.
    发明授权

    公开(公告)号:US10714440B2

    公开(公告)日:2020-07-14

    申请号:US16042644

    申请日:2018-07-23

    Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

    Fan-out semiconductor package
    3.
    发明授权

    公开(公告)号:US10403588B2

    公开(公告)日:2019-09-03

    申请号:US15402383

    申请日:2017-01-10

    Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

    Semiconductor package
    5.
    发明授权

    公开(公告)号:US11244921B2

    公开(公告)日:2022-02-08

    申请号:US16723588

    申请日:2019-12-20

    Abstract: A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.

    Fan-out sensor package
    6.
    发明授权

    公开(公告)号:US10700110B2

    公开(公告)日:2020-06-30

    申请号:US16132757

    申请日:2018-09-17

    Abstract: A fan-out sensor package includes: a substrate in which a through-hole is formed and portions of a wiring layer are exposed from an insulating layer; an image sensor having an active surface having a sensing region disposed below the through-hole of the substrate and connection pads disposed in the vicinity of the sensing region; an optical member disposed on the active surface of the image sensor; a dam member disposed in the vicinity of the sensing region; and an encapsulant encapsulating the substrate and the image sensor, wherein the third wiring layer and the connection pads are electrically connected to each other by connection members.

    Fan-out semiconductor package
    7.
    发明授权

    公开(公告)号:US10396049B2

    公开(公告)日:2019-08-27

    申请号:US15725179

    申请日:2017-10-04

    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer.

    Semiconductor package and board for mounting the same

    公开(公告)号:US10790239B2

    公开(公告)日:2020-09-29

    申请号:US16207053

    申请日:2018-11-30

    Abstract: A semiconductor package includes a semiconductor chip having an active surface on which connection pads are disposed and an inactive surface opposing the active surface, an encapsulant disposed to cover at least a portion of the semiconductor chip, and a connection member including a redistribution layer. The redistribution layer includes a plurality of first pads, a plurality of second pads surrounding the plurality of first pads, and a plurality of third pads surrounding the plurality of second pads. Each of the plurality of second pads and each of the plurality of third pads have shapes different from a shape of each of the plurality of first pads. Gaps between the plurality of second pads and gaps between the plurality of third pads are staggered with each other.

    Semiconductor package for reducing stress to redistribution via

    公开(公告)号:US10734342B2

    公开(公告)日:2020-08-04

    申请号:US15965590

    申请日:2018-04-27

    Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package and including an insulating member and a redistribution layer formed on the insulating member and having a redistribution via; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection member; UBM pads disposed on the passivation layer and overlapping the redistribution vias in the stacking direction; and UBM vias connecting the UBM pads to the redistribution layer through the passivation layer, not overlapping the redistribution vias with respect to the stacking direction, and having a non-circular cross section.

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