公开(公告)号：US20150269978A1

公开(公告)日：2015-09-24

申请号：US14218691

申请日：2014-03-18

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Rui Li ,  Sei Seung Yoon ,  Gregory Ameriada Uvieghara

IPC: G11C7/06 ,  G11C17/16

CPC classification number: G11C7/062 ,  G11C17/16 ,  G11C17/18 ,  H03F3/45183 ,  H03F3/45497 ,  H03F2203/45402 ,  H03F2203/45604 ,  H03F2203/45641 ,  H03F2203/45652

Abstract: A sense amplifier is disclosed that includes an amplifier circuit configured to receive, at an input, an input signal including an input level, the amplifier circuit configured to provide an amplified output signal including a gain with respect to the input level; and a feedback circuit coupled to receive the amplified output signal from the amplifier circuit, the feedback circuit configured to provide, at the input of the amplifier circuit, an adjusted version of the amplified output signal including a modified output magnitude based on common mode feedback.

Abstract translation: 公开了一种读出放大器，其包括放大器电路，其被配置为在输入端接收包括输入电平的输入信号，放大器电路被配置为提供包括相对于输入电平的增益的放大输出信号; 以及反馈电路，其耦合以从放大器电路接收放大的输出信号，所述反馈电路被配置为在放大器电路的输入处提供包括基于共模反馈的修改的输出幅度的经放大的输出信号的调整版本。

公开(公告)号：US09111589B2

公开(公告)日：2015-08-18

申请号：US14018404

申请日：2013-09-04

Applicant: QUALCOMM Incorporated

Inventor： Rakesh Kumar Sinha ,  Chirag Gulati ,  Ritu Chaba ,  Sei Seung Yoon

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/22

CPC classification number: G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/227

Abstract: Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.

Abstract translation: 公开了具有多字线设计的存储器的各种装置和方法。 存储器定时电路可以包括包括第一部分和第二部分的虚拟字线，并且还包括集中在伪字线的第二部分中的电容负载，连接到虚拟字线的第一部分的第一晶体管和 被配置为对所述虚拟字线充电;以及第二晶体管，连接到所述虚拟字线的第二部分，并且被配置为对所述虚拟字线进行放电。 一种方法可以包括使用第一晶体管对虚拟字线进行充电，以及使用第二晶体管对该虚拟字线进行放电，其中，所述虚拟字线包括第一部分和第二部分，并且还包括集中在所述第二部分中的电容负载 的虚拟字线。

公开(公告)号：US09082465B2

公开(公告)日：2015-07-14

申请号：US13765533

申请日：2013-02-12

Applicant: QUALCOMM Incorporated

Inventor： Balachander Ganesan ,  Ritu Chaba ,  Sei Seung Yoon

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C7/18

Abstract: A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line. A keeper circuit has an output coupled to the bit line to compensate for current leakage from the plurality of bit cells. The keeper circuit may comprise an n-channel metal-oxide-silicon (NMOS) transistor in series with a p-channel metal-oxide-silicon (PMOS) transistor.

Abstract translation: 提供一种存储器电路，其包括耦合到位线的多个位单元，其允许访问来自多个位单元中的每一个的信息。 感测反相器耦合到位线的输出端。 保持器电路具有耦合到位线的输出以补偿来自多个位单元的电流泄漏。 保持器电路可以包括与p沟道金属氧化物 - 硅（PMOS）晶体管串联的n沟道金属氧化物 - 硅（NMOS）晶体管。

公开(公告)号：US20150085554A1

公开(公告)日：2015-03-26

申请号：US14503861

申请日：2014-10-01

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

Abstract translation: 静态三元内容可寻址存储器（TCAM）包括密钥单元和耦合到中间匹配行的掩码单元。 关键单元耦合到第一下拉晶体管和第一上拉晶体管。 掩模单元耦合到第二下拉晶体管和第二上拉晶体管。 第一下拉晶体管和第二下拉晶体管并联连接，第一上拉晶体管和第二上拉晶体管串联连接。 匹配线输出还耦合到第一下拉晶体管和第二下拉晶体管，并且还耦合到第一上拉晶体管和第二上拉晶体管。

公开(公告)号：US08971096B2

公开(公告)日：2015-03-03

申请号：US13953473

申请日：2013-07-29

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Rakesh Vattikonda ,  Nishith Desai ,  Sei Seung Yoon

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16

Abstract: A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.

Abstract translation: 包括一对交叉耦合的反相器的多端口位单元通过在写入操作期间从电源和接地中选择性隔离交叉耦合的反相器中的第一个而提供增加的写入速度和增强的工作电压范围。 写入操作通过写入端口发生，该写入端口包括被配置为将由第一交叉耦合的反相器驱动的第一节点耦合到写入位线的传输门极。 位单元中的剩余的第二交叉耦合反相器被配置为驱动耦合到多个读端口的第二节点。

公开(公告)号：US20140369152A1

公开(公告)日：2014-12-18

申请号：US14472953

申请日：2014-08-29

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Gregory Ameriada Uvieghara ,  Sei Seung Yoon ,  Balachander Ganesan ,  Anil Chowdary Kota

IPC: H03K17/22 ,  H03K17/687 ,  G11C8/08

CPC classification number: H03K17/223 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0069 ,  G11C17/18 ,  H03K17/08104 ,  H03K17/6872 ,  H03K19/00315 ,  H03K2217/0018 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止电压损坏双模PMOS晶体管，尽管其尺寸相对较小，栅极氧化物厚度较薄。

公开(公告)号：US08860493B2

公开(公告)日：2014-10-14

申请号：US13799686

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu ,  Hari Ananthanarayanan ,  Venugopal Boynapalli

IPC: H03K17/00

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

公开(公告)号：US20140198598A1

公开(公告)日：2014-07-17

申请号：US13741886

申请日：2013-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Changho Jung ,  Peng Jin ,  Sei Seung Yoon

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/148 ,  G11C8/10

Abstract: The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus.

Abstract translation: 本公开涉及一种用于响应于一个或多个预解码地址线在对设备的至少一部分通电而被激活而停用存储器电路的一个或多个预解码地址线的装置。 具体地，该装置包括存储装置; 地址预解码器，被配置为基于输入地址激活多个预解码地址线中的一个或多个，其中所述多个预解码地址线耦合到所述存储器设备，用于访问与所述一个或多个激活的预解码的相关联的一个或多个存储器单元 地址线 以及上电复位电路，其被配置为响应于在对所述装置的所述至少一部分供电上启动的所述预解码地址线中的一个或多个来停用所述预解码地址线中的一个或多个。

公开(公告)号：US20140198588A1

公开(公告)日：2014-07-17

申请号：US13742964

申请日：2013-01-16

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Gregory Ameriada Uvieghara ,  Sei Seung Yoon ,  Balachander Ganesan ,  Anil Chowdary Kota

IPC: H03K17/22 ,  G11C7/12

CPC classification number: H03K17/223 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0069 ,  G11C17/18 ,  H03K17/08104 ,  H03K17/6872 ,  H03K19/00315 ,  H03K2217/0018 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

公开(公告)号：US10318726B2

公开(公告)日：2019-06-11

申请号：US15132026

申请日：2016-04-18

Applicant: QUALCOMM Incorporated

Inventor： Anil Kota ,  Sei Seung Yoon ,  Bhadri Kubendran

IPC: G06F21/55 ,  G06F21/64 ,  G06F3/06 ,  G06F11/10 ,  G06F11/263 ,  G06F21/78 ,  G11C17/14

Abstract: A method includes: reading a plurality of words from a one-time program (OTP) memory of a processing chip, wherein each of the words includes secure data for the chip and bits corresponding to a check pattern; comparing the bits corresponding to the check pattern to a preprogrammed check pattern; detecting an error based on comparing the bits corresponding to the check pattern to the preprogrammed check pattern; and performing an action by the processing chip in response to detecting the error.