公开(公告)号：US09666301B2

公开(公告)日：2017-05-30

申请号：US14488171

申请日：2014-09-16

Applicant: QUALCOMM Incorporated

Inventor： Venugopal Boynapalli ,  Kashyap Ramachandra Bellur ,  Prabaharan Balu ,  Bilal Zafar ,  Alex Dongkyu Park ,  Sei Seung Yoon

IPC: G01R31/28 ,  G11C29/08 ,  G11C29/32 ,  G11C8/16 ,  G11C29/20

CPC classification number: G11C29/08 ,  G11C8/16 ,  G11C29/20 ,  G11C29/32 ,  G11C2029/3202

Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.

公开(公告)号：US09570192B1

公开(公告)日：2017-02-14

申请号：US15061882

申请日：2016-03-04

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung Yoon ,  Anil Kota ,  Bjorn Grubelich

IPC: G11C8/00 ,  G11C17/16 ,  G11C8/08 ,  G11C8/10 ,  G11C7/06

CPC classification number: G11C17/16 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  G11C17/18

Abstract: A memory array includes a first subarray of memory cells and a second set of memory cells. The first and second subarrays of memory cells share a set of global word lines. The first and second subarrays of memory cells are coupled to first and second sets of bit lines, respectively. The first subarray includes rows of memory cells coupled to a first set of local word line drivers via a first set of local word lines, respectively. The second subarray includes rows of memory cells coupled to a second set of local word line drivers via a second set of local word lines, respectively. A selected local word line drivers generates a first asserted local word line signal for accessing at least one memory cell for reading or programming purpose in response to receiving a second asserted signal via a global word line and a third asserted signal.

Abstract translation: 存储器阵列包括存储器单元的第一子阵列和第二组存储器单元。 存储器单元的第一和第二子阵列共享一组全局字线。 存储单元的第一和第二子阵列分别耦合到第一和第二组位线。 第一子阵列分别包括经由第一组本地字线耦合到第一组本地字线驱动器的存储器单元行。 第二子阵列分别包括经由第二组本地字线耦合到第二组本地字线驱动器的存储器单元行。 选择的本地字线驱动器响应于经由全局字线和第三断言信号接收到第二被断言信号，产生用于访问至少一个存储器单元用于读取或编程目的的第一断言本地字线信号。

公开(公告)号：US09318165B2

公开(公告)日：2016-04-19

申请号：US14218691

申请日：2014-03-18

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Rui Li ,  Sei Seung Yoon ,  Gregory Ameriada Uvieghara

IPC: H03F3/45 ,  G11C7/06 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C7/062 ,  G11C17/16 ,  G11C17/18 ,  H03F3/45183 ,  H03F3/45497 ,  H03F2203/45402 ,  H03F2203/45604 ,  H03F2203/45641 ,  H03F2203/45652

Abstract: A sense amplifier is disclosed that includes an amplifier circuit configured to receive, at an input, an input signal including an input level, the amplifier circuit configured to provide an amplified output signal including a gain with respect to the input level; and a feedback circuit coupled to receive the amplified output signal from the amplifier circuit, the feedback circuit configured to provide, at the input of the amplifier circuit, an adjusted version of the amplified output signal including a modified output magnitude based on common mode feedback.

Abstract translation: 公开了一种读出放大器，其包括放大器电路，其被配置为在输入端接收包括输入电平的输入信号，放大器电路被配置为提供包括相对于输入电平的增益的放大输出信号; 以及反馈电路，其耦合以从放大器电路接收放大的输出信号，所述反馈电路被配置为在放大器电路的输入处提供包括基于共模反馈的修改的输出幅度的经放大的输出信号的调整版本。

公开(公告)号：US20150029782A1

公开(公告)日：2015-01-29

申请号：US13953473

申请日：2013-07-29

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Rakesh Vattikonda ,  Nishith Desai ,  Sei Seung Yoon

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16

Abstract: A multiport bitcell including a pair of cross-coupled inverters is provided with increased write speed and enhanced operating voltage range by the selective isolation of a first one of the cross-coupled inverters from a power supply and ground during a write operation. The write operation occurs through a write port that includes a transmission gate configured to couple a first node driven by the first cross-coupled inverter to a write bit line. A remaining second cross-coupled inverter in the bitcell is configured to drive a second node that couples to a plurality of read ports.

Abstract translation: 包括一对交叉耦合的反相器的多端口位单元通过在写入操作期间从电源和接地中选择性隔离交叉耦合的反相器中的第一个而提供增加的写入速度和增强的工作电压范围。 写入操作通过写入端口发生，该写入端口包括被配置为将由第一交叉耦合的反相器驱动的第一节点耦合到写入位线的传输门极。 位单元中的剩余的第二交叉耦合反相器被配置为驱动耦合到多个读端口的第二节点。

公开(公告)号：US20150029778A1

公开(公告)日：2015-01-29

申请号：US13953511

申请日：2013-07-29

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung Yoon ,  Chulmin Jung ,  Esin Terzioglu ,  Steven Millendorf

IPC: G11C17/12

CPC classification number: G11C17/12 ,  G11C7/24

Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word liens. Each memory cell includes a high Vt transistor and a low Vt transistor.

Abstract translation: 掩模编程的只读存储器（MROM）具有多个列线对，每一列具有位线和补码位线。 MROM包括与列线对和多个字留置权之间的多个交点相对应的多个存储单元。 每个存储单元包括高Vt晶体管和低Vt晶体管。

公开(公告)号：US20140321217A1

公开(公告)日：2014-10-30

申请号：US13919255

申请日：2013-06-17

Applicant: QUALCOMM Incorporated

Inventor： Hui Song ,  Sei Seung Yoon ,  Jongwon Lee

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/1012 ,  G11C7/18 ,  G11C2207/005

Abstract: The disclosure relates to an apparatus for reading data from a memory circuit that includes at least two memory banks. The apparatus includes a first multiplexer configured to generate data at a first output from a first selected one of a first set of bit lines of a first memory bank based on a select signal. The apparatus also includes a second multiplexer configured to generate data at a second output from a second selected one of a second set of bit lines of a second memory bank based on the select signal. Additionally, the apparatus includes a gating device configured to gate the data from either the first and second multiplexer outputs based on an enable signal. And, the apparatus includes an interface circuit configured to produce the gated data on a global bit line.

Abstract translation: 本公开涉及一种用于从包括至少两个存储体的存储器电路读取数据的装置。 该装置包括第一多路复用器，其被配置为基于选择信号从第一存储体组的第一组位线中的第一选定一个产生第一输出的数据。 该装置还包括第二多路复用器，其被配置为基于选择信号从第二存储器组的第二组位线中的第二选定的一个产生第二输出端的数据。 另外，该装置包括门控装置，其配置为基于使能信号来从第一和第二多路复用器输出端口选择数据。 并且，该装置包括被配置为在全局位线上产生门控数据的接口电路。

公开(公告)号：US20140266398A1

公开(公告)日：2014-09-18

申请号：US13799686

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu ,  Hari Ananthanarayanan ,  Venugopal Boynapalli

IPC: H03K17/00

CPC classification number: H03K17/002 ,  G11C7/02 ,  G11C7/10 ,  G11C7/1006

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract translation: 本发明提供一种半导体装置，用于在半导体装置中的第一装置和第二装置之间传输数据时降低功率。 向半导体装置添加附加电路以创建通信系统，该通信系统减少用于所有通信的第一设备和第二设备之间的数据总线的每个信号线的状态变化的数量。 附加电路包括解码器，其耦合以接收和转换来自第一设备的值，用于通过数据总线传输到向第二设备提供值的恢复（即重新编码）版本的编码器。 一个或多个多路复用器也可以包括在附加电路中以支持任何数量的设备。

公开(公告)号：US08830780B2

公开(公告)日：2014-09-09

申请号：US13741886

申请日：2013-01-15

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Peng Jin ,  Sei Seung Yoon

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/148 ,  G11C8/10

Abstract: The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus.

Abstract translation: 本公开涉及一种用于响应于一个或多个预解码地址线在对设备的至少一部分通电而被激活而停用存储器电路的一个或多个预解码地址线的装置。 具体地，该装置包括存储装置; 地址预解码器，被配置为基于输入地址激活多个预解码地址线中的一个或多个，其中所述多个预解码地址线耦合到所述存储器设备，用于访问与所述一个或多个激活的预解码的相关联的一个或多个存储器单元 地址线 以及上电复位电路，其被配置为响应于在对所述装置的所述至少一部分供电上启动的所述预解码地址线中的一个或多个来停用所述预解码地址线中的一个或多个。

公开(公告)号：US08787096B1

公开(公告)日：2014-07-22

申请号：US13742964

申请日：2013-01-16

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Gregory Ameriada Uvieghara ,  Sei Seung Yoon ,  Balachander Ganesan ,  Anil Chowdary Kota

IPC: G11C7/00 ,  G11C13/00

CPC classification number: H03K17/223 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0069 ,  G11C17/18 ,  H03K17/08104 ,  H03K17/6872 ,  H03K19/00315 ,  H03K2217/0018 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止电压损坏双模PMOS晶体管，尽管其尺寸相对较小，栅极氧化物厚度较薄。

公开(公告)号：US20140185348A1

公开(公告)日：2014-07-03

申请号：US13730487

申请日：2012-12-28

Applicant: QUALCOMM INCORPORATED

Inventor： Rakesh Vattikonda ,  Nishith Desai ,  ChangHo Jung ,  Sei Seung Yoon ,  Esin Terzioglu

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.

Abstract translation: 混合三元内容可寻址存储器（TCAM）内的方法包括将搜索词的第一部分与第一TCAM级中的存储字的第一部分进行比较。 该方法还包括将第一TCAM级的输出与第二TCAM级的输入进行接口。 该方法还包括当搜索词的第一部分与存储的单词的第一部分匹配时，在第二TCAM阶段中将搜索词的第二部分与所存储的单词的第二部分进行比较。 第一个TCAM阶段与第二个TCAM阶段不同。