公开(公告)号：US20140321217A1

公开(公告)日：2014-10-30

申请号：US13919255

申请日：2013-06-17

Applicant: QUALCOMM Incorporated

Inventor： Hui Song ,  Sei Seung Yoon ,  Jongwon Lee

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/1012 ,  G11C7/18 ,  G11C2207/005

Abstract: The disclosure relates to an apparatus for reading data from a memory circuit that includes at least two memory banks. The apparatus includes a first multiplexer configured to generate data at a first output from a first selected one of a first set of bit lines of a first memory bank based on a select signal. The apparatus also includes a second multiplexer configured to generate data at a second output from a second selected one of a second set of bit lines of a second memory bank based on the select signal. Additionally, the apparatus includes a gating device configured to gate the data from either the first and second multiplexer outputs based on an enable signal. And, the apparatus includes an interface circuit configured to produce the gated data on a global bit line.

Abstract translation: 本公开涉及一种用于从包括至少两个存储体的存储器电路读取数据的装置。 该装置包括第一多路复用器，其被配置为基于选择信号从第一存储体组的第一组位线中的第一选定一个产生第一输出的数据。 该装置还包括第二多路复用器，其被配置为基于选择信号从第二存储器组的第二组位线中的第二选定的一个产生第二输出端的数据。 另外，该装置包括门控装置，其配置为基于使能信号来从第一和第二多路复用器输出端口选择数据。 并且，该装置包括被配置为在全局位线上产生门控数据的接口电路。

公开(公告)号：US09165619B2

公开(公告)日：2015-10-20

申请号：US13919255

申请日：2013-06-17

Applicant: QUALCOMM Incorporated

Inventor： Hui Song ,  Sei Seung Yoon ,  Jongwon Lee

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C7/12 ,  G11C7/1012 ,  G11C7/18 ,  G11C2207/005

Abstract: The disclosure relates to an apparatus for reading data from a memory circuit that includes at least two memory banks. The apparatus includes a first multiplexer configured to generate data at a first output from a first selected one of a first set of bit lines of a first memory bank based on a select signal. The apparatus also includes a second multiplexer configured to generate data at a second output from a second selected one of a second set of bit lines of a second memory bank based on the select signal. Additionally, the apparatus includes a gating device configured to gate the data from either the first and second multiplexer outputs based on an enable signal. And, the apparatus includes an interface circuit configured to produce the gated data on a global bit line.

Abstract translation: 本公开涉及一种用于从包括至少两个存储体的存储器电路读取数据的装置。 该装置包括第一多路复用器，其被配置为基于选择信号从第一存储体组的第一组位线中的第一选定一个产生第一输出的数据。 该装置还包括第二多路复用器，其被配置为基于选择信号从第二存储器组的第二组位线中的第二选定的一个产生第二输出端的数据。 另外，该装置包括门控装置，其配置为基于使能信号来从第一和第二多路复用器输出端口选择数据。 并且，该装置包括被配置为在全局位线上产生门控数据的接口电路。