公开(公告)号：US09274891B2

公开(公告)日：2016-03-01

申请号：US14190103

申请日：2014-02-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/37

CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 解码方法包括：根据第一读取电压读取至少一个存储器单元以获得至少一个第一验证位; 执行根据第一验证位的硬比特模式解码过程，以及通过硬比特模式解码过程来确定是否产生第一有效码字; 如果第一有效码字不是由硬比特模式解码过程产生的，则获得存储单元的存储信息; 根据存储信息确定电压数; 根据与电压数相匹配的第二读取电压来读取存储器单元以获得第二验证位; 以及根据第二验证位执行软位模式解码过程。 因此，解码速度提高。

公开(公告)号：US09268634B2

公开(公告)日：2016-02-23

申请号：US14109959

申请日：2013-12-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1048

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一读取电压读取存储器单元以获得第一验证位; 执行包括根据第一验证位的概率解码算法的解码过程以获得第一解码比特，并且通过使用解码比特来确定解码是否成功; 如果解码失败，则根据第二读取电压读取存储器单元以获得第二验证位，并且根据第二验证位执行解码过程以获得第二解码位。 第二读取电压与第一读取电压不同，第二读取电压的数量等于第一读取电压的数量。 因此，能够提高校正误差的能力。

公开(公告)号：US09223648B2

公开(公告)日：2015-12-29

申请号：US13662541

申请日：2012-10-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Li-Chun Liang ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/27 ,  H03M13/29 ,  H03M13/11 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G11C7/1006 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/19 ,  H03M13/271 ,  H03M13/2778 ,  H03M13/2906

Abstract: A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.

Abstract translation: 提供了一种适用于可重写非易失性存储器模块的数据处理方法。 该方法包括接收第一数据流并对第一数据流执行纠错编码过程以产生对应于第一数据流的原始错误校验和校正（ECC）代码。 该方法还包括根据第二重排规则将原始ECC码转换成第二ECC码，并且原始ECC码与第二ECC码不同。 该方法还包括分别将第一数据流和第二ECC码写入可重写非易失性存储器模块中相同或不同的物理编程单元的数据位区和纠错码位区。

公开(公告)号：US20150331742A1

公开(公告)日：2015-11-19

申请号：US14307509

申请日：2014-06-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Li-Chun Liang ,  Kuo-Hsin Lai ,  Pei-Yu Shih ,  Tien-Ching Wang

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G06F11/106 ,  G06F11/1068 ,  G06F11/1076 ,  G11B20/1833 ,  G11C2029/0411

Abstract: A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command.

Abstract translation: 提供数据管理方法，以及存储器控制电路单元和使用该数据管理方法的存储器存储装置。 所述数据管理方法包括：根据第一读取命令从第一物理擦除单元读取第一数据流，其中所述第一数据流包括第一用户数据，第一纠错码和第一错误检测码。 该方法还包括：使用第一纠错码和错误检测码对第一用户数据进行解码，并确定第一用户数据是否被成功解码。 该方法还包括：如果第一用户数据被成功解码，则响应于第一读取命令，将通过将第一用户数据正确解码而获得的校正用户数据发送给主机系统。