公开(公告)号：US20170195597A1

公开(公告)日：2017-07-06

申请号：US14985122

申请日：2015-12-30

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara

IPC: H04N5/361 ,  H04N5/372 ,  H04N5/378

CPC classification number: H04N5/361 ,  H04N5/378

Abstract: A method for reducing ADC time for dark signals starts with pixel array capturing image data of frames including first frame and second frame. Pixel array includes visible pixels and black pixels (OPB). Scanning circuitry then selects OPB of first frame to be readout. OPB generate a dark signal when selected by scanning circuitry. Column readout circuitry included in readout circuitry then acquires the dark signal of first frame and processes the dark signal based on a ramp signal received from ramp generator included in readout circuitry to generate dark ADC output. Readout circuitry then determines a ramp timing offset based on the dark signal of first frame. The ramp timing offset is then applied to the second frame, which includes generating by the ramp generator the ramp signal for a second frame that includes the ramp timing offset. Other embodiments are described.

公开(公告)号：US12200389B2

公开(公告)日：2025-01-14

申请号：US18322408

申请日：2023-05-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara ,  Jiayu Guo ,  Liang Zuo ,  Lihang Fan

IPC: H04N25/78 ,  H03K3/037 ,  H03K5/22 ,  H03K5/24 ,  H03K19/20 ,  H04N25/616

Abstract: A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.

公开(公告)号：US12088937B2

公开(公告)日：2024-09-10

申请号：US17658559

申请日：2022-04-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Xuelian Liu ,  Min Qu ,  Liang Zuo ,  Selcuk Sen ,  Hiroaki Ebihara ,  Rui Wang ,  Lihang Fan

IPC: H04N25/709 ,  H04N25/78 ,  H04N25/704 ,  H04N25/75

CPC classification number: H04N25/709 ,  H04N25/78 ,  H04N25/704 ,  H04N25/75

Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.

公开(公告)号：US20230336891A1

公开(公告)日：2023-10-19

申请号：US17659045

申请日：2022-04-13

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara ,  Zhenfu Tian ,  Peter Bartkovjak ,  Satoshi Sakurai

IPC: H04N5/3745 ,  H03M1/56 ,  H03M1/12 ,  H03K5/24 ,  H04N17/00 ,  H04N5/378 ,  H04N5/369

CPC classification number: H04N5/37455 ,  H03M1/56 ,  H03M1/1245 ,  H03K5/24 ,  H04N17/002 ,  H04N5/378 ,  H04N5/3698

Abstract: A ramp buffer circuit includes a ramp buffer input device having an input coupled to receive a ramp signal. A current monitor is circuit coupled to a power line and the ramp buffer input device to generate a current monitor signal in response to an input current conducted through the ramp buffer input device. A corner bias circuit is coupled to the current monitor circuit to generate an assist bias voltage in response to the current monitor signal. A bias current source is coupled to an output of the ramp buffer input device. An assist current source is coupled to the corner bias circuit and coupled between the output of the ramp buffer input device and ground to conduct an assist current from the output of the ramp buffer input device to ground in response to the assist bias voltage.

公开(公告)号：US11770634B1

公开(公告)日：2023-09-26

申请号：US17719602

申请日：2022-04-13

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Zhenfu Tian ,  Hiroaki Ebihara ,  Tao Sun ,  Yi Liu ,  Shan Chen

IPC: H04N25/75 ,  H03K4/08 ,  H04N25/71 ,  H03M1/56 ,  H03K4/90 ,  H03M1/34

CPC classification number: H04N25/75 ,  H03K4/08 ,  H03K4/90 ,  H03M1/34 ,  H03M1/56 ,  H04N25/745

Abstract: A ramp generator includes an operational amplifier having an output to generate a ramp signal. An integration current source is coupled to a first input and a reference voltage is coupled to a second input of the operational amplifier. A feedback capacitor is coupled between the first input and the output of the operational amplifier. A monitor circuit is coupled to the first and second inputs of the operational amplifier to generate an output flag in response to a comparison of the first and second inputs. A trimming control circuit is configured to generate a trimming signal in response to the output flag. An assist current source is configured to conduct an assist current from the output of the operational amplifier to ground in response the trimming signal generated by the trimming control circuit.

公开(公告)号：US11683602B1

公开(公告)日：2023-06-20

申请号：US17716856

申请日：2022-04-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sangjoo Lee ,  Rui Wang ,  Xuelian Liu ,  Min Qu ,  Liang Zuo ,  Selcuk Sen ,  Hiroaki Ebihara ,  Lihang Fan

IPC: H04N25/615 ,  H04N25/133 ,  H04N25/13 ,  H04N25/447

CPC classification number: H04N25/6153 ,  H04N25/133 ,  H04N25/134 ,  H04N25/447

Abstract: An imaging device includes a pixel array of 1×3 pixel circuits that include 3 photodiodes in a column. Bitlines are coupled to the 1×3 pixel circuits. The bitlines are divided into groupings of 3 bitlines per column of the 1×3 pixel circuits. Each column of the 1×3 pixel circuits includes a plurality of first banks coupled to a first bitline, a plurality of second banks coupled to a second bitline, and a plurality of third banks coupled to a third bitline of a respective grouping of the 3 bitlines. The 1×3 pixel circuits are arranged into groupings of 3 1×3 pixel circuits per nine cell pixel structures that form a plurality of 3×3 pixel structures of the pixel array.

公开(公告)号：US11658202B2

公开(公告)日：2023-05-23

申请号：US17066200

申请日：2020-10-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tiejun Dai ,  Hiroaki Ebihara ,  Sang Joo Lee ,  Rui Wang ,  Hiroki Ui

IPC: H04N5/232 ,  H01L27/146 ,  H01L27/148 ,  H04N23/84 ,  H04N25/13 ,  H04N25/46 ,  H04N25/75 ,  H04N25/77

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14641 ,  H01L27/14812 ,  H01L27/14831 ,  H01L27/14868 ,  H04N23/84 ,  H04N25/13 ,  H04N25/46 ,  H04N25/75 ,  H04N25/77 ,  H01L27/14621

Abstract: A pixel array includes pixel cells, each including photodiodes. A source follower is coupled to generate an image signal in response image charge generated by the photodiodes. A first row select transistor is coupled to the source follower to output the image signal of the pixel cell. Pixel cells are organized into columns including a first column and a second column. The first row select transistors of the pixel cells of the first and second columns of pixel cells are coupled to first and second column bitlines, respectively. The pixel cells of the second column of pixel cells further include a second row select transistor coupled to the source follower to output the respective image signal to the first column bitline.

公开(公告)号：US11652131B2

公开(公告)日：2023-05-16

申请号：US17066277

申请日：2020-10-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sang Joo Lee ,  Rui Wang ,  Hiroaki Ebihara ,  Tiejun Dai ,  Hiroki Ui

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/374 ,  H01L27/148 ,  H04N9/04 ,  H04N5/347 ,  H04N5/3745

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14641 ,  H01L27/14812 ,  H01L27/14831 ,  H01L27/14868 ,  H04N5/347 ,  H04N5/378 ,  H04N5/3745 ,  H04N9/0451 ,  H04N9/04551 ,  H01L27/14621

Abstract: A pixel array includes pixel cells disposed in semiconductor material. Each of the pixel cells includes photodiodes, and a floating diffusion to receive image charge from the photodiodes. A source follower is coupled to the floating diffusion to generate an image signal in response image charge from the photodiodes. Drain regions of first and second row select transistors are coupled to a source of the source follower. A common junction is disposed in the semiconductor material between gates of the first and second row select transistors such that the drains of the first and second row select transistors are shared and coupled together through the semiconductor material of the common junction. The pixel cells are organized into a rows and columns with bitlines.

公开(公告)号：US20220201231A1

公开(公告)日：2022-06-23

申请号：US17127524

申请日：2020-12-18

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara ,  Chengcheng Xu

IPC: H04N5/378 ,  H03K5/24

Abstract: A comparator includes a first stage including a first output to generate a first output signal that transitions between an upper and lower voltage level in response to a comparison of first and second inputs of the first stage. A second stage includes an input coupled to receive the first output signal from the first output of the first stage, and a second output configured to generate a second output signal in response to the first output signal. A clamp circuit includes a first node and a second node. The first node is coupled to the first output of the first stage and the second node is coupled to a supply voltage. The clamp circuit is configured to clamp a voltage difference between the first node and the second node to clamp a voltage swing of the first output signal.

公开(公告)号：US20210152756A1

公开(公告)日：2021-05-20

申请号：US16685663

申请日：2019-11-15

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang ,  Hiroaki Ebihara ,  Zhiyong Zhan ,  Liang Zuo ,  Min Qu ,  Wanqing Xin ,  Xuelian Liu

IPC: H04N5/341 ,  H04N5/351 ,  H04N5/378

Abstract: An image sensor includes a pixel array with rows and columns of pixels. Each row of the pixel array has a first end that is opposite a second end of each row of the pixel array. Control circuitry is coupled to the first end of each row of the pixel array to provide control signals to each row of the pixel array from the first end of each row of the pixel array. Far end driver circuitry coupled to the second end of each row of the pixel array to selectively further drive from the second end of each row of the pixel array the control signals provided by the control circuitry from the first end of each row of the pixel array. The control circuitry is further coupled to provide far end control signals to the far end driver circuitry.