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公开(公告)号：US09710380B2
公开(公告)日：2017-07-18
申请号：US14013220
申请日：2013-08-29
Applicant: Intel Corporation
Inventor： Ren Wang , Kevin B. Theobald , Zeshan A. Chishti , Zhaojuan Bian , Aamer Jaleel , Tsung-Yuan C. Tai
IPC: G06F1/18 , G06F12/0811 , G06F12/0895
CPC classification number: G06F12/0811 , G06F12/0895 , G06F2212/1028 , G06F2212/601 , Y02D10/13
Abstract: Systems and methods for managing shared cache by multi-core processor. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a last level cache (LLC) slice; and a cache control logic coupled to the plurality of processing cores, the cache control logic configured to perform one of: making an LLC slice of an inactive processing core available to an active processing core or power gating the LLC slice, based on estimating cache requirements by active processing cores.
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公开(公告)号：US20170149926A1
公开(公告)日：2017-05-25
申请号：US15426718
申请日：2017-02-07
Applicant: Intel Corporation
Inventor： Ren Wang , Sameh Gobriel , Christian Maciocco , Tsung-Yuan C. Tai , Ben-Zion Friedman , Hang T. Nguyen , Namakkal N. Venkatesan , Michael A. O'Hanlon , Shrikant M. Shah , Sanjeev Jain
IPC: H04L29/08 , H04L12/743 , H04L12/721 , H04L12/24 , H04L12/741
CPC classification number: H04L67/2852 , H04L41/0893 , H04L45/38 , H04L45/745 , H04L45/7453 , H04L49/00
Abstract: Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.
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43.发明授权公开(公告)号：US09535483B2
公开(公告)日：2017-01-03
申请号：US13719880
申请日：2012-12-19
Applicant: Intel Corporation
Inventor： Alexander W. Min , Ren Wang , Jr-Shian Tsai , Tsung-Yuan Tsung-Yuan Tai
IPC: G06F1/32
CPC classification number: G06F1/3206
Abstract: Methods and systems may provide for determining whether a runtime disablement condition is met with respect to a sleep state and disabling the sleep state if the runtime disablement condition is met. Additionally, the sleep state may be enabled if a runtime reinstatement condition is met. In one example, determining whether the runtime disablement condition is met includes determining a false entry rate for the sleep state, and comparing the false entry rate to an energy-based threshold, wherein the sleep state is disabled if the false entry rate exceeds the energy-based threshold.
Abstract translation: 方法和系统可以提供用于确定是否满足休眠状态的运行时禁用条件并且如果满足运行时禁用条件则禁用休眠状态。 另外，如果满足运行时恢复条件，则可以启用睡眠状态。 在一个示例中，确定是否满足运行时禁用条件包括确定睡眠状态的错误进入率，以及将虚假进入率与基于能量的阈值进行比较，其中如果假进入速率超过能量，则禁用睡眠状态 的阈值。
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公开(公告)号：US09432916B2
公开(公告)日：2016-08-30
申请号：US13728314
申请日：2012-12-27
Applicant: Intel Corporation
Inventor： Alexander W. Min , Ren Wang , Jr-Shian Tsai , Tsung-Yuan C. Tai
CPC classification number: H04W48/16 , H04W48/04 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164
Abstract: Methods and systems may provide for determining a status of a mobile platform, wherein the status indicates whether the mobile platform is stationary, and adapting a detection schedule of one or more location sensors on the mobile platform based at least in part on whether the mobile platform is stationary. Additionally, one or more location updates may be generated based at least in part on information from the one or more location sensors. In one example, a location request is received, wherein the detection schedule is adapted further based on quality of service (QoS) information associated with the location request, and wherein the one or more location updates are generated in response to the location request.
Abstract translation: 方法和系统可以提供用于确定移动平台的状态，其中状态指示移动平台是否是静止的，以及在移动平台上适配一个或多个位置传感器的检测调度，至少部分地基于移动平台 是静止的 另外，可以至少部分地基于来自一个或多个位置传感器的信息来生成一个或多个位置更新。 在一个示例中，接收位置请求，其中所述检测调度还基于与所述位置请求相关联的服务质量（QoS）信息进行调整，并且其中响应于所述位置请求生成所述一个或多个位置更新。
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公开(公告)号：US20160092363A1
公开(公告)日：2016-03-31
申请号：US14496216
申请日：2014-09-25
Applicant: Intel Corporation
Inventor： Ren Wang , Tsung-Yuan C. Tai , Paul S. Diefenbaugh , Andrew J. Herdrich
CPC classification number: G06F11/3037 , G06F1/3206 , G06F1/3275 , G06F1/3287 , G06F11/3024 , G06F11/3058 , G06F11/3062 , G06F11/3409 , G06F11/3433 , G06F11/348 , G06F12/084 , G06F12/0895 , G06F2201/81 , G06F2201/88 , G06F2201/885 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D10/24 , Y02D10/34
Abstract: In one embodiment, a processor includes: a plurality of cores each to independently execute instructions; a shared cache memory coupled to the plurality of cores and having a plurality of clusters each associated with one or more of the plurality of cores; a plurality of cache activity monitors each associated with one of the plurality of clusters, where each cache activity monitor is to monitor one or more performance metrics of the corresponding cluster and to output cache metric information; a plurality of thermal sensors each associated with one of the plurality of clusters and to output thermal information; and a logic coupled to the plurality of cores to receive the cache metric information from the plurality of cache activity monitors and the thermal information and to schedule one or more threads to a selected core based at least in part on the cache metric information and the thermal information for the cluster associated with the selected core. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括：多个核，每个核独立地执行指令; 共享高速缓冲存储器，其耦合到所述多个核并具有多个簇，每个簇与所述多个核中的一个或多个相关联; 多个高速缓存活动监视器，每个与多个集群中的一个集群相关联，其中每个高速缓存活动监视器将监视相应集群的一个或多个性能度量并输出高速缓存量度信息; 多个热传感器，每个与所述多个群集中的一个簇相关联并输出热信息; 以及耦合到所述多个核的逻辑以从所述多个高速缓存活动监视器和所述热信息接收所述高速缓存度量信息，并且至少部分地基于所述高速缓存度量信息和所述热量来调度一个或多个线程到所选核心 与所选核心相关联的集群的信息。 描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US20140365797A1
公开(公告)日：2014-12-11
申请号：US14468041
申请日：2014-08-25
Applicant: Intel Corporation
Inventor： Ren Wang , Sanjay Rungta
IPC: G06F1/32
CPC classification number: G06F1/3206 , H04L65/80 , H04W28/0268 , H04W52/0232 , H04W52/0258 , Y02D70/142 , Y02D70/146
Abstract: A network interface device (NID) may determine whether the received data units of the computer system are to be compressed before transmitting the data units. The NID may determine the compression energy value consumed to compress the first K1 data units and a second transmission energy value to transmit the compressed first K1 data units. The NID may then estimate a first transmission energy value that may be consumed by the NID to transmit uncompressed first K1 data units using the second transmission energy value. The NID may then use the first and second transmission energy value and the compression energy value to determine if the remaining (N−K1) data units of the first data stream.
Abstract translation: 网络接口设备（NID）可以在发送数据单元之前确定计算机系统的接收数据单元是否被压缩。 NID可以确定压缩第一K1数据单元消耗的压缩能量值和第二传输能量值，以传送压缩的第一K1数据单元。 然后，NID可以估计可以由NID消耗的第一传输能量值，以使用第二传输能量值发送未压缩的第一K1数据单元。 然后，NID可以使用第一和第二传输能量值和压缩能量值来确定第一数据流的剩余（N-K1）个数据单元。
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公开(公告)号：US08902747B2
公开(公告)日：2014-12-02
申请号：US13631352
申请日：2012-09-28
Applicant: Intel Corporation
Inventor： Ren Wang , Sanjay Rungta
CPC classification number: G06F1/3206 , H04L65/80 , H04W28/0268 , H04W52/0232 , H04W52/0258 , Y02D70/142 , Y02D70/146
Abstract: A network interface device (NID) may determine whether the received data units of the computer system are to be compressed before transmitting the data units. The NID may determine the compression energy value consumed to compress the first K1 data units and a second transmission energy value to transmit the compressed first K1 data units. The NID may then estimate a first transmission energy value that may be consumed by the NID to transmit uncompressed first K1 data units using the second transmission energy value. The NID may then use the first and second transmission energy value and the compression energy value to determine if the remaining (N-K1) data units of the first data stream.
Abstract translation: 网络接口设备（NID）可以在发送数据单元之前确定计算机系统的接收数据单元是否被压缩。 NID可以确定压缩第一K1数据单元消耗的压缩能量值和第二传输能量值，以传送压缩的第一K1数据单元。 然后，NID可以估计可以由NID消耗的第一传输能量值，以使用第二传输能量值发送未压缩的第一K1数据单元。 然后，NID可以使用第一和第二传输能量值和压缩能量值来确定第一数据流的剩余（N-K1）个数据单元。
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48.发明授权公开(公告)号：US11816036B2
公开(公告)日：2023-11-14
申请号：US17738919
申请日：2022-05-06
Applicant: Intel Corporation
Inventor： Anil Vasudevan , Venkata Krishnan , Andrew J. Herdrich , Ren Wang , Robert G. Blankenship , Vedaraman Geetha , Shrikant M. Shah , Marshall A. Millier , Raanan Sade , Binh Q. Pham , Olivier Serres , Chyi-Chang Miao , Christopher B. Wilkerson
IPC: G06F12/0868 , G06F12/0897 , G06F3/06 , G06F12/0811 , G06F12/0871
CPC classification number: G06F12/0868 , G06F3/065 , G06F3/068 , G06F3/0619 , G06F12/0811 , G06F12/0871 , G06F12/0897 , G06F2212/1024 , G06F2212/283 , G06F2212/311 , G06F2212/6046
Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.
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公开(公告)号：US11486719B2
公开(公告)日：2022-11-01
申请号：US16941163
申请日：2020-07-28
Applicant: Intel Corporation
Inventor： Ren Wang , Zhonghong Ou , Arvind Kumar , Kristoffer Fleming , Tsung-Yuan C. Tai , Timothy J. Gresham , John C. Weast , Corey Kukis
IPC: G01C21/34 , H04W4/024 , H04W4/029 , H04B17/318 , H04W24/08
Abstract: Examples disclosed herein include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data.
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50.发明申请公开(公告)号：US20220261351A1
公开(公告)日：2022-08-18
申请号：US17738919
申请日：2022-05-06
Applicant: Intel Corporation
Inventor： Anil Vasudevan , Venkata Krishnan , Andrew J. Herdrich , Ren Wang , Robert G. Blankenship , Vedaraman Geetha , Shrikant M. Shah , Marshall A. Millier , Raanan Sade , Binh Q. Pham , Olivier Serres , Chyi-Chang Miao , Christopher B. Wilkerson
IPC: G06F12/0868 , G06F12/0897 , G06F3/06 , G06F12/0811 , G06F12/0871
Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.
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