公开(公告)号：US20060110912A1

公开(公告)日：2006-05-25

申请号：US10995923

申请日：2004-11-22

申请人： Yung-Cheng Lu ,  Tien-I Bao ,  Su-Hong Lin ,  Syun-Ming Jang

发明人： Yung-Cheng Lu ,  Tien-I Bao ,  Su-Hong Lin ,  Syun-Ming Jang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76834

摘要： Semiconductor devices with composite etch stop layers and methods of fabrication thereof. An semiconductor device with a composite etch stop layer includes a substrate having a conductive member, a first etch stop layer on the substrate and the conductive member, a second etch stop layer and a dielectric layer sequentially over the second etch stop layer, having a conductive layer therein down through the dielectric layer, the second etch stop layer and the first etch stop layer to the conductive member.

摘要翻译： 具有复合蚀刻停止层的半导体器件及其制造方法。 具有复合蚀刻停止层的半导体器件包括具有导电部件的衬底，衬底上的第一蚀刻停止层和导电部件，在第二蚀刻停止层上顺序地具有第二蚀刻停止层和介电层，具有导电 在其中向下穿过介电层，第二蚀刻停止层和第一蚀刻停止层到达导电构件。

公开(公告)号：US20050156317A1

公开(公告)日：2005-07-21

申请号：US11056459

申请日：2005-02-11

申请人： Wai-Fan Yau ,  David Cheung ,  Shin-Puu Jeng ,  Kuowei Liu ,  Yung-Cheng Lu

发明人： Wai-Fan Yau ,  David Cheung ,  Shin-Puu Jeng ,  Kuowei Liu ,  Yung-Cheng Lu

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76834 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76837

摘要： A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.

摘要翻译： 一种通过有机硅烷化合物和氧化性气体反应沉积低介电常数膜的方法和装置。 氧化的有机硅烷膜具有优异的阻挡性能，用作与其它电介质层相邻的衬垫层或盖层。 氧化的有机硅烷膜也可以用作制造双镶嵌结构的蚀刻停止层或金属间介质层。 氧化的有机硅烷膜也提供了不同介电层之间的极好的粘附性。 优选的氧化有机硅烷膜是通过甲基硅烷，CH 3 3 SiH 3 N 2和N 2 O 2的反应制备的。

公开(公告)号：US20050098896A1

公开(公告)日：2005-05-12

申请号：US10706156

申请日：2003-11-12

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Yih-Hsiung Lin ,  Tien-I Bao ,  Bi-Trong Chen ,  Yung-Cheng Lu

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Yih-Hsiung Lin ,  Tien-I Bao ,  Bi-Trong Chen ,  Yung-Cheng Lu

IPC分类号： H01L23/532 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer. The first, second and third low-dielectric constant materials sub-layers are preferably comprised of the same material, deposited continuously in one or more deposition chambers while the deposition conditions such as the gas flow rate, power, or gas species are adjusted or changed.

摘要翻译： 用于多层互连层间介电层（ILD）的结构，其制造方法以及包括ILD层的半导体器件。 ILD层包括第一低介电常数材料子层和设置在第一低介电常数材料子层上的第二低介电常数材料子层。 第二低介电常数材料子层与第一低介电常数材料子层具有至少一种不同的材料特性。 第三低介电常数材料子层设置在第二低介电常数材料副层上，第三低介电常数材料子层与第二低介电常数材料子层具有至少一种不同的材料特性 -层。 第一，第二和第三低介电常数材料子层优选由相同的材料组成，其连续沉积在一个或多个沉积室中，同时调节或改变诸如气体流速，功率或气体种类的沉积条件 。

公开(公告)号：US06753607B1

公开(公告)日：2004-06-22

申请号：US10441511

申请日：2003-05-19

申请人： Zhen-Cheng Wu ,  Yung-Cheng Lu ,  Syun-Ming Jang

发明人： Zhen-Cheng Wu ,  Yung-Cheng Lu ,  Syun-Ming Jang

IPC分类号： H01L2348

CPC分类号： H01L21/02126 ,  H01L21/02312 ,  H01L21/31051 ,  H01L21/31633 ,  H01L21/76829

摘要： The present invention relates to an improved integrated circuit structure including adjacent conductive and dielectric layers having a continuous, planar top surface, produced by a process which includes treating the surface with a silane compound, followed by depositing an etch stop layer over the surface, wherein a glue layer is not applied to the surface.

摘要翻译： 本发明涉及一种改进的集成电路结构，其包括具有连续的平坦顶表面的相邻的导电和电介质层，其通过包括用硅烷化合物处理表面的方法产生，然后在表面上沉积蚀刻停止层，其中 胶层不施加到表面。

公开(公告)号：US06541282B1

公开(公告)日：2003-04-01

申请号：US09594187

申请日：2000-06-13

申请人： David Cheung ,  Wai-Fan Yau ,  Robert P. Mandal ,  Shin-Puu Jeng ,  Kuo-Wei Liu ,  Yung-Cheng Lu ,  Michael Barnes ,  Ralf B. Willecke ,  Farhad Moghadam ,  Tetsuya Ishikawa ,  Tze Wing Poon

发明人： David Cheung ,  Wai-Fan Yau ,  Robert P. Mandal ,  Shin-Puu Jeng ,  Kuo-Wei Liu ,  Yung-Cheng Lu ,  Michael Barnes ,  Ralf B. Willecke ,  Farhad Moghadam ,  Tetsuya Ishikawa ,  Tze Wing Poon

IPC分类号： H05H102

CPC分类号： H01L21/76835 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2221/1031 ,  Y10T428/24926 ,  Y10T428/31663

摘要： A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas at a constant RF power level from about 10 W to about 200 W or a pulsed RF power level from about 20 W to about 500 W. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organosilane film is produced by reaction of methylsilane, CH3SiH3, or dimethylsilane, (CH3)2SiH2, and nitrous oxide, N2O; at a constant RF power level from about 10 W to about 150 W, or a pulsed RF power level from about 20 W to about 250 W during 10% to 30% of the duty cycle.

摘要翻译： 一种用于通过有机硅化合物和氧化性气体以约10W至约200W的恒定RF功率水平的反应沉积低介电常数膜的方法和设备或从约20W至约500W的脉冲RF功率水平。 在与有机硅化合物混合之前，优选在单独的微波室内可以提高氧化气体的离解，以帮助控制沉积膜的碳含量。 氧化的有机硅烷或有机硅氧烷膜具有良好的屏障性能，用作邻近其它介电层的衬垫层或盖层。 氧化的有机硅烷或有机硅氧烷膜也可以用作蚀刻停止层和用于制造双镶嵌结构的金属间介电层。 氧化的有机硅烷或有机硅氧烷膜也在不同的介电层之间提供优异的粘附性。 优选的氧化有机硅烷膜是通过甲基硅烷，CH 3 SiH 3或二甲基硅烷，（CH 3）2 SiH 2和一氧化二氮，N 2 O的反应制备的; 在约10W至约150W的恒定RF功率水平或在占空比的10％至30％期间从约20W至约250W的脉冲RF功率水平。

公开(公告)号：US20080171431A1

公开(公告)日：2008-07-17

申请号：US11654427

申请日：2007-01-17

申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部电介质层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下比在顶部电介质层中留下的孔密度更低的孔密度，这导致底部电介质层中较高的介电值k。

公开(公告)号：US20070264843A1

公开(公告)日：2007-11-15

申请号：US11430623

申请日：2006-05-09

申请人： Lih-Ping Li ,  Yung-Cheng Lu ,  Tien-I. Bao ,  Syun-Ming Jang ,  Ying-Tsung Chen

发明人： Lih-Ping Li ,  Yung-Cheng Lu ,  Tien-I. Bao ,  Syun-Ming Jang ,  Ying-Tsung Chen

IPC分类号： H01L21/31

CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31604 ,  H01L21/76829

摘要： A method for manufacturing an integrated circuit is provided. In one example, the method includes forming a substantially nitrogen-free silicon carbide layer over a substrate using a methyl silicate gas.

摘要翻译： 提供一种用于制造集成电路的方法。 在一个实例中，该方法包括使用甲基硅酸盐气体在基底上形成基本上无氮的碳化硅层。

公开(公告)号：US07256124B2

公开(公告)日：2007-08-14

申请号：US11094011

申请日：2005-03-30

申请人： Keng-Chu Lin ,  Yi-Chi Liao ,  Hung-Chun Tsai ,  Yung-Cheng Lu ,  Hung-Wen Su

发明人： Keng-Chu Lin ,  Yi-Chi Liao ,  Hung-Chun Tsai ,  Yung-Cheng Lu ,  Hung-Wen Su

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76825

摘要： A method of fabricating a semiconductor device. A semiconductor substrate with a patterned conductive layer on a top surface of the substrate is first provided. A dielectric layer is then formed to cover the substrate. Thereafter, an electron beam irradiation procedure is performed to anneal the patterned conductive layer and reduce resistance of the patterned conductive layer.

摘要翻译： 一种制造半导体器件的方法。 首先提供在基板的顶表面上具有图案化导电层的半导体衬底。 然后形成介电层以覆盖基板。 此后，执行电子束照射程序以退火图案化导电层并降低图案化导电层的电阻。

公开(公告)号：US07220677B2

公开(公告)日：2007-05-22

申请号：US11106120

申请日：2005-04-13

申请人： Lin-Ping Li ,  Yung-Cheng Lu ,  Wen-Chih Chiou ,  Chih-Hsien Lin

发明人： Lin-Ping Li ,  Yung-Cheng Lu ,  Wen-Chih Chiou ,  Chih-Hsien Lin

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L22/10 ,  G01R31/2831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer.

摘要翻译： 一种用于形成多级半导体器件以在WAT测试之后消除导电互连突起的方法，所述方法包括形成第一金属化层; 进行晶圆验收测试（WAT）工艺; 然后在金属化层上进行化学机械抛光（CMP）。

公开(公告)号：US07217648B2

公开(公告)日：2007-05-15

申请号：US11020372

申请日：2004-12-22

申请人： Yung-Cheng Lu ,  Ying-Tsung Chen ,  Zhen-Cheng Wu ,  Pi-Tsung Chen

发明人： Yung-Cheng Lu ,  Ying-Tsung Chen ,  Zhen-Cheng Wu ,  Pi-Tsung Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L2221/1047

摘要： A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene copper conductor and depositing a semipermeable cap layer. In alternative embodiments, the cap layer consists essentially of silicon carbide, silicon nitride, Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof. The semipermeable cap layer is preferably deposited under PECVD conditions such that the cap layer is sufficiently permeable to enable removal of porogen degradation by-products. Preferred embodiments further include an in-situ N2/NH3 treatment before depositing the semipermeable cap layer.

摘要翻译： 提供一种制造具有多孔低k电介质层的半导体器件的方法。 优选的实施方案包括在镶嵌工艺中形成含致孔剂的低k电介质层的步骤。 在优选的实施方案中，通过电子束致孔剂降解的孔产生在CMP平坦化镶嵌铜导体并沉积半透膜盖层的步骤之后发生。 在替代实施例中，盖层基本上由碳化硅，氮化硅，Co，W，Al，Ta，Ti，Ni，Ru及其组合组成。 半透膜盖层优选在PECVD条件下沉积，使得盖层具有足够的可渗透性以能够除去致孔剂降解副产物。 优选实施方案还包括在沉积半透膜盖层之前的原位N 2 / NH 3 N 3处理。