公开(公告)号：US20090148932A1

公开(公告)日：2009-06-11

申请号：US11952984

申请日：2007-12-07

Applicant: Thaddeus Gabara

Inventor： Thaddeus Gabara

IPC: G01N1/28

CPC classification number: G01N13/00 ,  G01N13/02 ,  H01L2224/48227 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A LoC (Lab on a Chip) is described to analyze surface properties of fluid drops. Substrates with cavities near the edge are filled with fluids that have a contact angle greater than 90°. The surfaces of two different drops can be brought in contact with one another by using Coulomb forces. Several experiments can be carried out while the drops are in contact: the concentration of the fluid in each drop can be altered, tangential and normal forces can be applied to the contact surface, voltage differences across and current flow through the contact surface can be monitored. MEMS pumps can be used to mix reagents or buffers with the fluid to determine the protein concentration or to extract DNA from whole cells, respectively. Substrates holding optical components can be used to align fibers with either lasers or receivers. The alignment is automatic and controlled by a control unit.

Abstract translation: 描述了LoC（芯片实验室）来分析液滴的表面性质。 具有靠近边缘的空腔的衬底填充有接触角大于90°的流体。 两个不同液滴的表面可以通过使用库仑力相互接触。 可以在液滴接触时进行几个实验：可以改变每个液滴中的流体浓度，可以将切向和法向力施加到接触表面，可监测通过接触表面的电流差异和流过接触表面的电流。 。 可以使用MEMS泵将试剂或缓冲液与流体混合以确定蛋白质浓度或分别从全细胞中提取DNA。 保持光学部件的基板可用于将光纤与激光器或接收器对准。 对位是自动的，由控制单元控制。

公开(公告)号：US20090147433A1

公开(公告)日：2009-06-11

申请号：US11953008

申请日：2007-12-07

Applicant: Thaddeus Gabara

Inventor： Thaddeus Gabara

IPC: H05F3/00

CPC classification number: H01L21/6833 ,  H01L23/645 ,  H01L24/12 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/11526 ,  H01L2223/6677 ,  H01L2224/13021 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8083 ,  H01L2224/81143 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/95145 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/203 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02252 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/0002

Abstract: At least one non-volatile device is coupled to a first Coulomb island. The floating gates of these non-volatile devices are connected to the island and can charge the Coulomb islands. One device can charge the island positively while a second device can be used to charge the island negatively. The Coulomb island can have a small probe opening where a charge can be introduced by using mechanical means such as an external probe or a MEMS switch. A fully charged capacitor formed in a first substrate can provide additional energy to a levitated substrate if the first substrate is connected to the levitated substrate. Bonding wires can be attached to a substrate that is attached to a mother substrate. Then, Coulomb forces can levitate the substrate from the mother substrate and the bonding wires can provide a source of power to the levitated substrate.

Abstract translation: 至少一个非易失性装置耦合到第一库仑岛。 这些非易失性装置的浮动栅极连接到岛上并且可以对库仑岛进行充电。 一个设备可以正确地对岛进行充电，而第二个设备可以用来对岛负价。 库仑岛可以具有小的探针开口，通过使用诸如外部探针或MEMS开关的机械装置可以引入电荷。 形成在第一衬底中的完全充电的电容器可以向悬浮衬底提供额外的能量，如果第一衬底连接到悬浮衬底。 接合线可以附接到附着到母基板的基板上。 然后，库仑力可以从母基板悬浮基板，接合线可以向悬浮基板提供动力源。

公开(公告)号：US20090145229A1

公开(公告)日：2009-06-11

申请号：US11952963

申请日：2007-12-07

Applicant: Thaddeus Gabara

Inventor： Thaddeus Gabara

IPC: G01P15/125

CPC classification number: G01P15/125 ,  B60R2021/01211 ,  G01P15/18 ,  H01L2224/48227 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

Abstract: Coulomb islands are charged to create Coulomb forces which are applied between a first and second substrate. The Coulomb islands are used to levitate the first substrate over the second substrate into an equilibrium position. A processing unit monitors the values of capacitors formed between the substrates to provide feedback information to maintain the first substrate in this equilibrium position. The first substrate can be an accelerometer that can be used to calculate the direction and magnitude of a deceleration. The processing unit sends the digital information to a bus coupled to a plurality of air bags. The digital information identifies the appropriate air bags that need to be enabled to minimize the impact of a crash. Vertical changes in acceleration can also be detected making this invention applicable for flight vehicles.

Abstract translation: 充电库仑岛以产生施加在第一和第二基底之间的库仑力。 库仑群岛用于将第二基板上的第一基板悬浮到平衡位置。 处理单元监视形成在基板之间的电容器的值，以提供反馈信息，以将第一基板保持在该平衡位置。 第一基板可以是可用于计算减速度的方向和幅度的加速度计。 处理单元将数字信息发送到耦合到多个安全气囊的总线。 数字信息识别需要启用的适当气囊，以尽量减少碰撞的影响。 也可以检测加速度的垂直变化，使本发明适用于飞行器。

公开(公告)号：US20070180650A1

公开(公告)日：2007-08-09

申请号：US11349764

申请日：2006-02-08

Applicant: Thaddeus Gabara

Inventor： Thaddeus Gabara

IPC: A47L5/14

CPC classification number: A47L9/08

Abstract: The basic invention uses a positive air pressure port to loosen foreign objects into a cavity and a negative air pressure port to vacuum these objects from the cavity. The positive air pressure port can be used as a substitute for a mechanical beater brush. Removing the beater brush allows the weight of the housing unit to be reduced. The number of positive air pressure ports can be reduced to increase the exit velocity of the air flow out of a single port focusing the energy of the compressed air to a smaller area of the surface which loosens hard to remove foreign objects from the surface. A motor can be used to sweep a single positive air pressure port in a back and fort motion to automatically clean the surface. Finally, the housing unit can be made transparent to view the surface as it is being cleaned.

Abstract translation: 本发明使用正空气压力端口将异物放入空腔和负空气压力端口，以从空腔中吸收这些物体。 正气压端口可用作机械搅拌刷的替代品。 拆下打浆刷可以减少外壳单元的重量。 可以减少正空气压力端口的数量，以增加空气流出单个端口的出口速度，将压缩空气的能量聚焦到表面的较小区域，其松散以从表面去除异物。 电机可以用于在后面和后面的运动中扫描单个正气压端口，以自动清洁表面。 最后，外壳单元可以做成透明的，以便在清洁表面时观察表面。

公开(公告)号：US20070170957A1

公开(公告)日：2007-07-26

申请号：US11677053

申请日：2007-02-21

Applicant: Thaddeus Gabara

Inventor： Thaddeus Gabara

IPC: H03K5/22

CPC classification number: G06F1/10 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B27/00 ,  H03B2200/0076

Abstract: CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or μprocessor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. Several frequency-adjusting techniques are presented which can be used in an distributed clock network environment which includes an array of oscillators. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of oscillators are described.

Abstract translation: CMOS LC槽电路和电感之间的磁链可用于在VLSI芯片或处理器的表面上分布和传播时钟信号。 油箱回路提供了一种绝热的行为，可回收无功元件之间的能量，并将传统意义上的损耗降至最低。 磁通联动可以用于编排一些看似独立和分布的CMOS LC电路，以作为一个单元。 提出了可以在包括振荡器阵列的分布式时钟网络环境中使用的几种频率调整技术。 描述了振荡器频率调节的无源磁链，机械和有限状态机技术。

公开(公告)号：US20070018767A1

公开(公告)日：2007-01-25

申请号：US11184767

申请日：2005-07-19

Applicant: Thaddeus Gabara

Inventor： Thaddeus Gabara

IPC: H01F5/00

CPC classification number: H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/16145 ,  H01L2924/19015 ,  H01L2924/19042 ,  H01L2924/19104

Abstract: Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.

Abstract translation: 电感或电阻并联使得电感或电阻的组合值根据并联组合规则减小。 本发明通过将多个电感器并联放置来降低电感器的寄生电阻。 此外，通过仔细放置这些电感器，可以使用这些电感器之间的互感将等效电感值增加到接近单个电感器的原始电感值的值。 因此，可以产生具有低得​​多的寄生电阻值的电感。 本发明允许形成高Q电感器，并且对于需要电感的任何电路设计将是有益的。 本发明的另一方面是可以将线圈分隔以最小化涡流损耗。 本发明可以容易地在平面技术中实现。 几个电路的仿真表明，与常规技术相比，功耗可以减少3到4倍。

公开(公告)号：US20060107245A1

公开(公告)日：2006-05-18

申请号：US10988083

申请日：2004-11-12

Applicant: Kanad Chakraborty ,  Thaddeus Gabara ,  Kevin Stiles ,  Bingxiong Xu

Inventor： Kanad Chakraborty ,  Thaddeus Gabara ,  Kevin Stiles ,  Bingxiong Xu

IPC: G06F17/50 ,  G06F9/45

CPC classification number: G06F17/505

Abstract: A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net is examined to check whether the crosstalk glitch is primarily due to propagated noise from an earlier stage or due to noise injected in the selected victim net. If the crosstalk glitch is propagated from an earlier stage, then a second static latch is inserted before the state in which the first static latch is inserted. Alternatively, another static latch may be inserted in the selected victim net. Cell libraries including a variety of static latch circuit architectures can be designed.

Abstract translation: 静态锁存电路用于抑制同步数字集成电路中的串扰毛刺。 将静态锁存器插入到所选择的受害网络中，并且如果被选择的受害者网络中引起的串扰毛刺被充分抑制，则检查网络。 如果不是，则检查所选择的受害网络以检查串扰毛刺是否主要是由于来自较早阶段的传播噪声或由于在所选择的受害者网络中注入的噪声引起的。 如果从较早阶段传播串扰毛刺，则在插入第一静态锁存器的状态之前插入第二静态锁存器。 或者，可以在所选择的受害网络中插入另一个静态锁存器。 可以设计包括各种静态锁存电路结构的单元库。

公开(公告)号：US20060103456A1

公开(公告)日：2006-05-18

申请号：US10990368

申请日：2004-11-18

Applicant: Kouros Azimi ,  Thaddeus Gabara

Inventor： Kouros Azimi ,  Thaddeus Gabara

IPC: H03K5/00

CPC classification number: H03H11/405 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1237 ,  H03B2201/025 ,  H03H11/483 ,  H03J2200/10

Abstract: A variable capacitance circuit on an integrated circuit comprises a MOS transistor, and a capacitance multiplier connected to one end of a channel of the MOS device. A MOS device is formed in series with an inductance, and a capacitance multiplier is formed to be connected to a node between the MOS device and the inductance.

Abstract translation: 集成电路中的可变电容电路包括MOS晶体管和连接到MOS器件的沟道的一端的电容倍增器。 与电感串联形成MOS器件，并且形成电容倍增器以连接到MOS器件和电感之间的节点。

公开(公告)号：US20050079654A1

公开(公告)日：2005-04-14

申请号：US11002608

申请日：2004-12-02

Applicant: Thaddeus Gabara ,  Tarek Jomaa

Inventor： Thaddeus Gabara ,  Tarek Jomaa

IPC: G03F1/08 ,  G06F17/50 ,  H01L21/027 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L21/44

CPC classification number: H01L21/76838 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the comers as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

Abstract translation: 提供集成电路制造技术，其允许非水平/非垂直导线横穿整个芯片表面，而不仅仅是常规曼哈顿几何形状中的角落，同时互连电路点。 这通过在IC制造操作期间使用关于互连层或电平的可变旋转分配方法来实现。 因此，这些技术消除了光刻步骤问题，减少了互连距离并减轻了互连线之间的电容相互作用的影响。