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    Batching modified blocks to the same dram page
    41.
    发明授权
    Batching modified blocks to the same dram page 有权
    将修改的块批处理到同一个戏剧页面

    公开(公告)号：US09529718B2

    公开(公告)日：2016-12-27

    申请号：US14569175

    申请日：2014-12-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Syed Ali R. Jafri ,  Yasuko Eckert ,  Srilatha Manne ,  Mithuna S. Thottethodi ,  Gabriel H. Loh

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/0833 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/121 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/62 ,  Y02D10/13

    Abstract: To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the cost of opening and closing DRAM pages. A desirable approach is batch write backs to the same DRAM page by retaining modified blocks in the cache until a sufficient number of modified blocks belonging to the same memory page are ready for write backs.

    Abstract translation: 为了有效地将数据从高速缓存传输到存储器，期望将与存储器中的相同页面相对应的更多数据加载到行缓冲器中。 将数据写入当前未加载到行缓冲区的内存页面时，需要关闭旧页面并打开新页面。 两种操作都消耗能量和时钟周期，并可能延迟更多关键的存储器读取请求。 因此，期望具有多于一个写入同一DRAM页面的写入以分摊打开和关闭DRAM页面的成本。 期望的方法是通过将修改的块保留在高速缓存中来批量回写到相同的DRAM页面，直到属于同一存储器页面的足够数量的修改的块准备好回写。

    SELECTING A RESOURCE FROM A SET OF RESOURCES FOR PERFORMING AN OPERATION
    42.
    发明申请
    SELECTING A RESOURCE FROM A SET OF RESOURCES FOR PERFORMING AN OPERATION 有权
    从一组资源中选择一个资源来执行操作

    公开(公告)号：US20160062803A1

    公开(公告)日：2016-03-03

    申请号：US14935056

    申请日：2015-11-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

    IPC: G06F9/50 ,  G06F12/08

    CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

    Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.

    Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制在从一组表中选择的表中执行查找以从资源集合中识别资源。 当资源不可用于执行操作并且直到选择用于执行操作的另一资源为止时，选择机制识别表中的下一个资源，并且当下一个资源可用于执行操作时选择用于执行操作的下一个资源 。

    Cache Bypassing Policy Based on Prefetch Streams
    43.
    发明申请
    Cache Bypassing Policy Based on Prefetch Streams 审中-公开
    基于预取流的缓存旁路策略

    公开(公告)号：US20160041914A1

    公开(公告)日：2016-02-11

    申请号：US14451929

    申请日：2014-08-05

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Gabriel Loh

    IPC: G06F12/08

    CPC classification number: G06F12/0862 ,  G06F12/0888 ,  G06F2212/602 ,  G06F2212/6046 ,  Y02D10/13

    Abstract: Embodiments include methods, systems, and computer readable medium directed to cache bypassing based on prefetch streams. A first cache receives a memory access request. The request references data in the memory. The data comprises non-reuse data. After a determination of a miss in the first cache, the first cache forwards the memory access request to a cache control logic. The detection of the non-reuse data instructs the cache control logic to allocate a block only in a second cache and bypass allocating a block in the first cache. The first cache is closer to the memory than the second cache.

    Abstract translation: 实施例包括基于预取流的针对缓存旁路的方法，系统和计算机可读介质。 第一缓存接收存储器访问请求。 请求引用内存中的数据。 数据包括非重用数据。 在确定第一缓存中的未命中之后，第一缓存将存储器访问请求转发到高速缓存控制逻辑。 非重用数据的检测指示高速缓存控制逻辑仅在第二高速缓存中分配块，并且绕过在第一高速缓存中分配块。 第一个缓存比第二个缓存更接近内存。

    Selecting a resource from a set of resources for performing an operation
    44.
    发明授权
    Selecting a resource from a set of resources for performing an operation 有权
    从一组用于执行操作的资源中选择资源

    公开(公告)号：US09183055B2

    公开(公告)日：2015-11-10

    申请号：US13761985

    申请日：2013-02-07

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

    IPC: G06F9/46 ,  G06F9/50

    CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

    Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism is configured to perform a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the identified resource is not available for performing the operation and until a resource is selected for performing the operation, the selection mechanism is configured to identify a next resource in the table and select the next resource for performing the operation when the next resource is available for performing the operation.

    Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制被配置为在从一组表中选择的表中执行查找，以从资源集合中识别资源。 当所识别的资源不可用于执行操作并且直到选择资源来执行操作时，选择机制被配置为识别表中的下一个资源，并且当下一个资源可用时选择用于执行操作的下一个资源 用于执行操作。

    MECHANISMS TO BOUND THE PRESENCE OF CACHE BLOCKS WITH SPECIFIC PROPERTIES IN CACHES
    45.
    发明申请
    MECHANISMS TO BOUND THE PRESENCE OF CACHE BLOCKS WITH SPECIFIC PROPERTIES IN CACHES 有权
    在缓存中具有特定属性的高速缓存块的存在机制

    公开(公告)号：US20140181414A1

    公开(公告)日：2014-06-26

    申请号：US14055869

    申请日：2013-10-16

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Gabriel H. Loh ,  Mauricio Breternitz ,  James M. O'Connor ,  Srilatha Manne ,  Nuwan S. Jayasena ,  Mithuna S. Thottethodi

    IPC: G06F12/08

    CPC classification number: G06F12/0808 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0848 ,  G06F12/0888 ,  G06F12/0897 ,  Y02D10/13 ,  Y02D10/14

    Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.

    Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，其中第一存储体断电。 作为响应，向第二组写入请求，指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。 如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。 如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。 高速缓存控制器将这些数据写入较低级别的内存。

    SPILL DATA MANAGEMENT
    46.
    发明申请
    SPILL DATA MANAGEMENT 审中-公开
    泄漏数据管理

    公开(公告)号：US20140164708A1

    公开(公告)日：2014-06-12

    申请号：US13708090

    申请日：2012-12-07

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Mauricio Breternitz, JR. ,  James M. O'Connor ,  Srilatha Manne ,  Yasuko Eckert

    IPC: G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/0875 ,  G06F12/0891 ,  G06F12/123 ,  Y02D10/13

    Abstract: A processor discards spill data from a memory hierarchy in response to the final access to the spill data has been performed by a compiled program executing at the processor. In some embodiments, the final access determined based on a special-purpose load instruction configured for this purpose. In some embodiments the determination is made based on the location of a stack pointer indicating that a method of the executing program has returned, so that data of the returned method that remains in the stack frame is no longer to be accessed. Because the spill data is discarded after the final access, it is not transferred through the memory hierarchy.

    Abstract translation: 响应于对处理器执行的编译程序已经执行对溢出数据的最终访问，处理器从存储器层次结构中丢弃溢出数据。 在一些实施例中，基于为此目的配置的专用加载指令确定最终访问。 在一些实施例中，基于指示执行程序的方法已经返回的堆栈指针的位置进行确定，使得保留在堆栈帧中的返回的方法的数据不再被访问。 由于溢出数据在最终访问后被丢弃，因此不会通过内存层次结构传输。

    Look-ahead teleportation for reliable computation in multi-SIMD quantum processor
    48.
    发明授权
    Look-ahead teleportation for reliable computation in multi-SIMD quantum processor 有权

    公开(公告)号：US12079634B2

    公开(公告)日：2024-09-03

    申请号：US16794124

    申请日：2020-02-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Onur Kayiran ,  Jieming Yin ,  Yasuko Eckert

    IPC: G06F9/38 ,  G06F8/41 ,  G06N10/00

    CPC classification number: G06F9/3887 ,  G06F8/41 ,  G06N10/00

    Abstract: A technique for processing qubits in a quantum computing device is provided. The technique includes determining that, in a first cycle, a first quantum processing region is to perform a first quantum operation that does not use a qubit that is stored in the first quantum processing region, identifying a second quantum processing region that is to perform a second quantum operation at a second cycle that is later than the first cycle, wherein the second quantum operation uses the qubit, determining that between the first cycle and the second cycle, no quantum operations are performed in the second quantum processing region, and moving the qubit from the first quantum processing region to the second quantum processing region.

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