Invention Application
US20140181414A1 MECHANISMS TO BOUND THE PRESENCE OF CACHE BLOCKS WITH SPECIFIC PROPERTIES IN CACHES
有权
在缓存中具有特定属性的高速缓存块的存在机制
- Patent Title: MECHANISMS TO BOUND THE PRESENCE OF CACHE BLOCKS WITH SPECIFIC PROPERTIES IN CACHES
- Patent Title (中): 在缓存中具有特定属性的高速缓存块的存在机制
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Application No.: US14055869Application Date: 2013-10-16
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Publication No.: US20140181414A1Publication Date: 2014-06-26
- Inventor: Yasuko Eckert , Gabriel H. Loh , Mauricio Breternitz , James M. O'Connor , Srilatha Manne , Nuwan S. Jayasena , Mithuna S. Thottethodi
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.
Public/Granted literature
- US09251069B2 Mechanisms to bound the presence of cache blocks with specific properties in caches Public/Granted day:2016-02-02
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