公开(公告)号：US12169758B2

公开(公告)日：2024-12-17

申请号：US17491304

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Salonik Resch ,  Anthony Gutierrez ,  Yasuko Eckert ,  Vedula Venkata Srikant Bharadwaj ,  Mark H. Oskin

IPC: G06F9/48 ,  G06F11/36 ,  G06N10/00

Abstract: An electronic device includes a quantum processor having a plurality of qubits and a processor. The processor runs a plurality of instances of a quantum program substantially in parallel on the quantum processor using a separate set of qubits from among the plurality of qubits for each instance of the quantum program. The processor then acquires an output for each instance of the quantum program from the quantum processor. The processor next uses the outputs for generating an output of the quantum program.

公开(公告)号：US20230094508A1

公开(公告)日：2023-03-30

申请号：US17491304

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Salonik Resch ,  Anthony Gutierrez ,  Yasuko Eckert ,  Vedula Venkata Srikant Bharadwaj ,  Mark H. Oskin

IPC: G06N10/00 ,  G06F11/36 ,  G06F9/48

Abstract: An electronic device includes a quantum processor having a plurality of qubits and a processor. The processor runs a plurality of instances of a quantum program substantially in parallel on the quantum processor using a separate set of qubits from among the plurality of qubits for each instance of the quantum program. The processor then acquires an output for each instance of the quantum program from the quantum processor. The processor next uses the outputs for generating an output of the quantum program.

公开(公告)号：US11550627B2

公开(公告)日：2023-01-10

申请号：US17215171

申请日：2021-03-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony Gutierrez ,  Sooraj Puthoor

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/38

Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

公开(公告)号：US11086809B2

公开(公告)日：2021-08-10

申请号：US16693638

申请日：2019-11-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony Gutierrez

IPC: G06F13/36 ,  G06F13/362 ,  G06F11/34 ,  G06F11/30

Abstract: Data transfer acceleration includes receiving, by a data transfer accelerator in a first node of a plurality of nodes, from a second node of the plurality of nodes, a request for data in a second state, wherein the second node stores an instance of the data in a first state; generating a message including one or more operations to transform the data from the first state to the second state; and sending the message to the second node in response to the request.

公开(公告)号：US11989591B2

公开(公告)日：2024-05-21

申请号：US17037727

申请日：2020-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony Gutierrez ,  Vedula Venkata Srikant Bharadwaj ,  Yasuko Eckert ,  Mark H. Oskin

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F9/4401

CPC classification number: G06F9/505 ,  G06F9/30043 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/4403 ,  G06F9/4418

Abstract: A dynamically configurable overprovisioned microprocessor optimally supports a variety of different compute application workloads and with the capability to tradeoff among compute performance, energy consumption, and clock frequency on a per-compute application basis, using general-purpose microprocessor designs. In some embodiments, the overprovisioned microprocessor comprises a physical compute resource and a dynamic configuration logic configured to: detect an activation-warranting operating condition; undarken the physical compute resource responsive to detecting the activation-warranting operating condition; detect a configuration-warranting operating condition; and configure the overprovisioned microprocessor to use the undarkened physical compute resource responsive to detecting the configuration-warranting operating condition.

公开(公告)号：US11797410B2

公开(公告)日：2023-10-24

申请号：US17526218

申请日：2021-11-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Shrikanth Ganapathy ,  Yasuko Eckert ,  Anthony Gutierrez ,  Karthik Ramu Sangaiah ,  Vedula Venkata Srikant Bharadwaj

IPC: G06F15/80 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3051 ,  G06F11/3024 ,  G06F15/80 ,  G06F11/3409 ,  Y02D10/00

Abstract: A processor includes a controller and plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for the chiplets that identifies a performance of each chiplet at each of a plurality of performance levels for specified sets of processor cores on that chiplet. The controller receives an identification of one or more selected chiplets from among the plurality of chiplets for which a specified number of processor cores are to be configured at a given performance level, the one or more selected chiplets having been selected based on the chiplet-level performance information and performance requirements. The controller configures the specified number of processor cores of the one or more selected chiplets at the given performance level. A task is then run on the specified number of processor cores of the one or more selected chiplets at the given performance level.

公开(公告)号：US20230097115A1

公开(公告)日：2023-03-30

申请号：US17485662

申请日：2021-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony Gutierrez ,  Sooraj Puthoor

IPC: G06F9/50 ,  G06F12/02

Abstract: A processing system executes a specialized wavefront, referred to as a “garbage collecting wavefront” or GCWF, to identify and deallocate resources such as, for example, scalar registers, vector registers, and local data share space, that are no longer being used by wavefronts of a workgroup executing at the processing system (i.e., dead resources). In some embodiments, the GCWF is programmed to have compiler information regarding the resource requirements of the other wavefronts of the workgroup and specifies the program counter after which there will be a permanent drop in resource requirements for the other wavefronts. In other embodiments, the standard compute wavefronts signal the GCWF when they have completed using resources. The GCWF sends a command to deallocate the dead resources so the dead resources can be made available for additional wavefronts.

公开(公告)号：US20220188208A1

公开(公告)日：2022-06-16

申请号：US17118404

申请日：2020-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony Gutierrez ,  Yasuko Eckert ,  Sergey Blagodurov ,  Jagadish B. Kotra

IPC: G06F11/30 ,  G06F1/20 ,  G06F12/0815 ,  G11C11/406 ,  G06F9/48 ,  G06F9/30

Abstract: A method may include, in response to a change in an operating parameter of a processing unit, modifying a signal pathway to a processing circuit component of the processing unit, and communicating with the processing circuit component via the signal pathway.

公开(公告)号：US12131186B2

公开(公告)日：2024-10-29

申请号：US17993490

申请日：2022-11-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony Gutierrez ,  Sooraj Puthoor

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/3877 ,  G06F9/542 ,  G06F9/545 ,  G06F9/546

Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

公开(公告)号：US11875425B2

公开(公告)日：2024-01-16

申请号：US17134904

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sooraj Puthoor ,  Bradford Beckmann ,  Nuwan Jayasena ,  Anthony Gutierrez

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06T1/20 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/545 ,  G06T2210/52

Abstract: Implementing heterogeneous wavefronts on a graphics processing unit (GPU) is disclosed. A scheduler assigns heterogeneous wavefronts for execution on a compute unit of a processing device. The heterogeneous wavefronts include different types of wavefronts such as vector compute wavefronts and service-level wavefronts that vary in resource requirements and instruction sets. As one example, heterogeneous wavefronts may include scalar wavefronts and vector compute wavefronts that execute on scalar units and vector units, respectively. Distinct sets of instructions are executed for the heterogeneous wavefronts on the compute unit. Heterogeneous wavefronts are processed in the same pipeline of the processing device.