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    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT
    41.
    发明申请
    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20190326272A1

    公开(公告)日：2019-10-24

    申请号：US15958169

    申请日：2018-04-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brett P. Wilkerson ,  Milind Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

    IPC: H01L25/18 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00

    Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

    GLASS CORE PACKAGE SUBSTRATES
    42.
    发明申请
    GLASS CORE PACKAGE SUBSTRATES 有权

    公开(公告)号：US20250029900A1

    公开(公告)日：2025-01-23

    申请号：US18784143

    申请日：2024-07-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Deepak Vasant Kulkarni ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Chintan Buch

    IPC: H01L23/495 ,  H01L23/14 ,  H10B12/00

    Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

    DOUBLE SIDE TRANSISTORS ON SAME SILICON WAFER
    43.
    发明公开
    DOUBLE SIDE TRANSISTORS ON SAME SILICON WAFER 审中-公开

    公开(公告)号：US20240038596A1

    公开(公告)日：2024-02-01

    申请号：US17873591

    申请日：2022-07-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Chandra Sekhar Mandalapu ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Richard T. Schultz

    IPC: H01L21/84 ,  H01L21/02 ,  H01L23/14 ,  H01L23/498 ,  H01L27/12

    CPC classification number: H01L21/84 ,  H01L21/02164 ,  H01L23/147 ,  H01L23/49827 ,  H01L27/1203

    Abstract: An apparatus and method for efficiently increasing semiconductor chip functionality in a particular area. A semiconductor fabrication process (or process) grows a silicon substrate layer, and forms multiple p-type and n-type transistors along a front side surface of the silicon substrate layer. The process flips the silicon substrate layer and removes silicon substrate leaving a particular thickness of the silicon substrate layer. The process forms multiple p-type and n-type transistors along the back side surface of the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the back side surface to particular signals. The process forms through silicon vias (TSVs) that traverse through the silicon substrate layer. The process again flips the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the front side surface to particular signals.

    SEMICONDUCTOR CHIP DEVICE
    46.
    发明公开
    SEMICONDUCTOR CHIP DEVICE 审中-公开

    公开(公告)号：US20230187364A1

    公开(公告)日：2023-06-15

    申请号：US17644191

    申请日：2021-12-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Chia-Hao Cheng ,  Kong Toon Ng ,  Rahul Agarwal ,  Brett P. Wilkerson

    IPC: H01L23/538 ,  H01L21/48

    CPC classification number: H01L23/5384 ,  H01L21/486

    Abstract: An embodiment of a semiconductor chip device can include a molding layer having a first side and a second side, an interconnect chip at least partially encased in the molding layer, the interconnect chip comprising a through substrate via (TSV) that extends through the interconnect chip, an insulating layer positioned on the first side of the molding layer, and a conductive structure that is positioned vertically below the interconnect chip and extends through the insulating layer, wherein the conductive structure is electrically coupled to the TSV.

    Integrated circuit package with integrated voltage regulator
    49.
    发明授权
    Integrated circuit package with integrated voltage regulator 有权

    公开(公告)号：US11011466B2

    公开(公告)日：2021-05-18

    申请号：US16367731

    申请日：2019-03-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Chia-Hao Cheng

    IPC: H01L23/52 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

    Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

    SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS
    50.
    发明申请
    SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS 有权

    公开(公告)号：US20210098441A1

    公开(公告)日：2021-04-01

    申请号：US16586309

    申请日：2019-09-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John J. Wuu ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Rahul Agarwal

    IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

    Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.

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