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    SEMICONDUCTOR CHIP DEVICE
    7.
    发明公开
    SEMICONDUCTOR CHIP DEVICE 审中-公开

    公开(公告)号：US20230187364A1

    公开(公告)日：2023-06-15

    申请号：US17644191

    申请日：2021-12-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Chia-Hao Cheng ,  Kong Toon Ng ,  Rahul Agarwal ,  Brett P. Wilkerson

    IPC: H01L23/538 ,  H01L21/48

    CPC classification number: H01L23/5384 ,  H01L21/486

    Abstract: An embodiment of a semiconductor chip device can include a molding layer having a first side and a second side, an interconnect chip at least partially encased in the molding layer, the interconnect chip comprising a through substrate via (TSV) that extends through the interconnect chip, an insulating layer positioned on the first side of the molding layer, and a conductive structure that is positioned vertically below the interconnect chip and extends through the insulating layer, wherein the conductive structure is electrically coupled to the TSV.

    Integrated circuit package with integrated voltage regulator
    8.
    发明授权
    Integrated circuit package with integrated voltage regulator 有权

    公开(公告)号：US11011466B2

    公开(公告)日：2021-05-18

    申请号：US16367731

    申请日：2019-03-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Chia-Hao Cheng

    IPC: H01L23/52 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

    Abstract: Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.

    FAN-OUT PACKAGE WITH REINFORCING RIVETS
    9.
    发明申请
    FAN-OUT PACKAGE WITH REINFORCING RIVETS 有权

    公开(公告)号：US20210057352A1

    公开(公告)日：2021-02-25

    申请号：US16544021

    申请日：2019-08-19

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah ,  Chia-Hao Cheng ,  Brett P. Wilkerson ,  Lei Fu

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.

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