公开(公告)号：US08664678B2

公开(公告)日：2014-03-04

申请号：US13167286

申请日：2011-06-23

Applicant: Yasunari Ooyabu ,  Toshitaka Nakamura ,  Hironaka Fujii ,  Hisataka Ito

Inventor： Yasunari Ooyabu ,  Toshitaka Nakamura ,  Hironaka Fujii ,  Hisataka Ito

IPC: H01L33/44

CPC classification number: C09K11/7774 ,  B32B5/16 ,  B32B9/005 ,  B32B2250/03 ,  B32B2250/40 ,  B32B2262/105 ,  B32B2264/107 ,  B32B2307/50 ,  B32B2307/732 ,  B32B2457/14 ,  C04B35/44 ,  C04B2235/3225 ,  C04B2235/3229 ,  C04B2235/764 ,  C09K11/025 ,  H01L33/44 ,  H01L33/505 ,  H01L33/507 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  Y10T428/263 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A phosphor ceramic includes at least one fluorescent layer that is capable of emitting fluorescent light; and at least one non-fluorescent layer that does not emit fluorescent light and is laminated onto the fluorescent layer.

Abstract translation: 荧光体陶瓷包括能够发射荧光的至少一个荧光层; 以及至少一个不发射荧光并层叠在荧光层上的非荧光层。

公开(公告)号：US20120262054A1

公开(公告)日：2012-10-18

申请号：US13446568

申请日：2012-04-13

Applicant: Yasunari OOYABU ,  Hisataka ITO ,  Toshiki NAITO

Inventor： Yasunari OOYABU ,  Hisataka ITO ,  Toshiki NAITO

IPC: H01J1/62 ,  B32B3/24 ,  B29C65/76 ,  H01J5/16

CPC classification number: H01L33/56 ,  H01L24/97 ,  H01L33/505 ,  H01L33/60 ,  H01L2224/16225 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2933/005 ,  Y10T156/11 ,  Y10T428/24322 ,  H01L2924/00

Abstract: A reflecting resin sheet provides a reflecting resin layer at the side of a light emitting diode element and includes a first release substrate and the reflecting resin layer provided on one surface in a thickness direction of the first release substrate. In the first release substrate and the reflecting resin layer, a through hole extending therethrough in the thickness direction is formed corresponding to the light emitting diode element so as to allow an inner circumference surface of the through hole in the reflecting resin layer to be disposed in opposed relation to a side surface of the light emitting diode element.

Abstract translation: 反射树脂片在发光二极管元件的一侧提供反射树脂层，并且包括第一释放基板和设置在第一释放基板的厚度方向的一个表面上的反射树脂层。 在第一释放基板和反射树脂层中，对应于发光二极管元件形成在厚度方向上延伸穿过的通孔，以使反射树脂层中的通孔的内周表面设置在 与发光二极管元件的侧表面相对。

公开(公告)号：US20120261699A1

公开(公告)日：2012-10-18

申请号：US13446517

申请日：2012-04-13

Applicant: Yasunari OOYABU ,  Tsutomu NISHIOKA ,  Hisataka ITO ,  Toshiki NAITO

Inventor： Yasunari OOYABU ,  Tsutomu NISHIOKA ,  Hisataka ITO ,  Toshiki NAITO

IPC: H01L33/50 ,  H01L33/60 ,  F21V7/00

CPC classification number: H01L33/60 ,  H01L24/97 ,  H01L25/0753 ,  H01L33/505 ,  H01L33/54 ,  H01L33/56 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2933/0041 ,  H01L2933/005 ,  H01L2933/0058 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A reflecting resin sheet provides a reflecting resin layer at the side of a light emitting diode element. The reflecting resin sheet includes a release substrate and the reflecting resin layer provided on one surface in a thickness direction of the release substrate. The reflecting resin layer is formed corresponding to the light emitting diode element so as to be capable of being in close contact with the light emitting diode element.

Abstract translation: 反射树脂片在发光二极管元件的一侧提供反射树脂层。 反射树脂片包括剥离基板和设置在剥离基板的厚度方向的一个表面上的反射树脂层。 对应于发光二极管元件形成反射树脂层，以便能够与发光二极管元件紧密接触。

公开(公告)号：US08179691B2

公开(公告)日：2012-05-15

申请号：US12318689

申请日：2009-01-06

Applicant: Takahiko Yokai ,  Tetsuya Ohsawa ,  Yasunari Ooyabu

Inventor： Takahiko Yokai ,  Tetsuya Ohsawa ,  Yasunari Ooyabu

IPC: H05K7/00

CPC classification number: H05K1/0245 ,  G11B5/484 ,  G11B5/486 ,  H05K1/0216 ,  H05K1/0248 ,  H05K1/056 ,  H05K2201/0352 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09736

Abstract: A wired circuit board includes a first insulating layer; a first wire formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first wire; and a second wire formed on the second insulating layer so as to be arranged in opposed relation to the first wire in a thickness direction. The thickness of the first wire is 1 μm or less and is ⅓ or less of the thickness of the second insulating layer.

Abstract translation: 布线电路板包括第一绝缘层; 形成在所述第一绝缘层上的第一线; 形成在所述第一绝缘层上以覆盖所述第一线的第二绝缘层; 以及形成在所述第二绝缘层上以在厚度方向上相对于所述第一布线布置的第二布线。 第一线的厚度为1μm以下，为第二绝缘层的厚度的1/3以下。

公开(公告)号：US08071886B2

公开(公告)日：2011-12-06

申请号：US12004400

申请日：2007-12-21

Applicant: Jun Ishii ,  Yasunari Ooyabu ,  Yasuhito Funada

Inventor： Jun Ishii ,  Yasunari Ooyabu ,  Yasuhito Funada

IPC: H05K1/00

CPC classification number: H05K1/0259 ,  G11B5/486 ,  H05K1/056 ,  H05K1/167 ,  Y10T29/49117

Abstract: A wired circuit board includes a metal supporting board, an insulating layer formed on the metal supporting board, a conductive pattern formed on the insulating layer and having a plurality of wires, and a semiconductive layer formed on a surface of the insulating layer exposed from the conductive pattern so as to be in contact with the conductive pattern. The insulating layer is formed with a groove exposing the metal supporting board between at least two adjacent wires, and the semiconductive layer is in contact with the metal supporting board in the groove.

Abstract translation: 布线电路板包括金属支撑板，形成在金属支撑板上的绝缘层，形成在绝缘层上并具有多根导线的导电图案，以及形成在绝缘层的暴露于该绝缘层的表面上的半导体层 导电图案以与导电图案接触。 绝缘层形成有将金属支撑板暴露在至少两个相邻导线之间的沟槽，并且半导电层与凹槽中的金属支撑板接触。

公开(公告)号：US08015703B2

公开(公告)日：2011-09-13

申请号：US12081835

申请日：2008-04-22

Applicant: Hitoki Kanagawa ,  Tetsuya Ohsawa ,  Yasunari Ooyabu

Inventor： Hitoki Kanagawa ,  Tetsuya Ohsawa ,  Yasunari Ooyabu

IPC: H01R9/00 ,  H05K3/00

CPC classification number: H05K1/112 ,  G11B5/4833 ,  H01L2224/11003 ,  H01L2224/742 ,  H05K1/056 ,  H05K3/06 ,  H05K3/244 ,  H05K3/28 ,  H05K3/363 ,  H05K3/44 ,  H05K2201/0394 ,  H05K2201/09063 ,  H05K2201/0969 ,  H05K2201/10666 ,  H05K2203/0323 ,  H05K2203/041 ,  H05K2203/0455 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49204

Abstract: A method of manufacturing a wired circuit board including a metal supporting board. An insulating layer is formed on the metal supporting board in a pattern in which concave portions are formed. A conductive pattern in a pattern having terminals for connecting with external terminals via a molten metal is formed on the metal supporting board and the insulating layer. The terminals include shoulder portions corresponding to the concave portions and are concaved downward from an upper surface. First through holes penetrate the terminals in a thickness direction thereof Second through holes are formed communicating with the first through holes in portions of the insulating layer corresponding to the terminals by removing the concave portions to expose a lower surface of the terminals such that the second through holes penetrate the insulating layer in a thickness direction thereof and have a diameter larger than that of the first through holes.

Abstract translation: 一种制造包括金属支撑板的布线电路板的方法。 绝缘层以形成有凹部的图案形成在金属支撑板上。 在金属支撑板和绝缘层上形成具有用于经由熔融金属与外部端子连接的端子的图案中的导体图案。 端子包括对应于凹部的肩部，并且从上表面向下凹入。 第一通孔在厚度方向上贯穿端子。通过除去凹部以露出端子的下表面，在绝缘层的与端子对应的部分中的第一通孔形成第二通孔，以使第二通孔 孔的厚度方向穿过绝缘层，其直径大于第一通孔的直径。

公开(公告)号：US07747123B2

公开(公告)日：2010-06-29

申请号：US12358528

申请日：2009-01-23

Applicant: Takami Hikita ,  Kazunori Mune ,  Toshiki Naitou ,  Yasunari Ooyabu

Inventor： Takami Hikita ,  Kazunori Mune ,  Toshiki Naitou ,  Yasunari Ooyabu

IPC: G02B6/12 ,  G02B6/10 ,  B29D11/00

CPC classification number: G02B6/122 ,  G02B6/10 ,  G02B6/1221 ,  G02B6/13 ,  G02B6/132 ,  G02B6/136 ,  G02B6/43 ,  H05K1/0274 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/048 ,  H05K3/107 ,  H05K3/281 ,  H05K2203/0723

Abstract: A method of manufacturing an opto-electric hybrid board which is capable of reducing the number of steps for the manufacture of the opto-electric hybrid board and which achieves the reduction in thickness of the opto-electric hybrid board to be manufactured, and an opto-electric hybrid board obtained thereby. A resist layer is formed on a core-forming resin layer, and is then formed into a predetermined pattern. Resultant portions of the core-forming resin layer serve as cores (optical interconnect lines) 3. Next, a thin metal film 5 is formed on the under cladding layer 2 so as to cover the resist layer and the cores 3. Thereafter, the resist layer is removed together with portions of the thin metal film 5 lying on the surface of the resist layer. Electroplating is performed on the remaining portions of the thin metal film 5 to fill grooves 6 defined between adjacent ones of the cores 3 with electroplated layers 7a obtained by the electroplating. The electroplated layers 7a serve as electrical interconnect lines 7.

Abstract translation: 一种制造光电混合基板的方法，其能够减少制造光电混合基板的步骤数量，并且能够实现要制造的光电混合基板的厚度的减小，以及光电 电动混合板。 在芯成型树脂层上形成抗蚀剂层，然后形成预定图案。 芯部形成树脂层的有效部分用作芯（光学互连线）3.接下来，在下敷层2上形成薄膜5，以覆盖抗蚀剂层和芯3.然后，将抗蚀剂 层与位于抗蚀剂层的表面上的薄金属膜5的一部分一起被去除。 对薄金属膜5的剩余部分进行电镀，以通过电镀获得的电镀层7a填充在相邻的芯3之间限定的槽6。 电镀层7a用作电互连线7。

公开(公告)号：US07616846B2

公开(公告)日：2009-11-10

申请号：US12358946

申请日：2009-01-23

Applicant: Takami Hikita ,  Kazunori Mune ,  Toshiki Naitou ,  Yasunari Ooyabu

Inventor： Takami Hikita ,  Kazunori Mune ,  Toshiki Naitou ,  Yasunari Ooyabu

IPC: G02B6/12 ,  G02B6/10

CPC classification number: G02B6/122 ,  G02B6/10 ,  G02B6/1221 ,  G02B6/13 ,  G02B6/132 ,  G02B6/136 ,  G02B6/43 ,  H05K1/0274 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/107 ,  H05K3/28 ,  H05K2203/0723

Abstract: A method of manufacturing an opto-electric hybrid board which is capable of reducing the number of steps for the manufacture of the opto-electric hybrid board and which achieves the reduction in thickness of the opto-electric hybrid board to be manufactured, and an opto-electric hybrid board obtained thereby. A plurality of protruding cores (optical interconnect lines) 3 are formed in a predetermined pattern. Thereafter, a thin metal film 4 is formed in grooves defined between adjacent ones of the cores 3. Via-filling plating is performed on the thin metal film 4 to fill the above-mentioned grooves with a via-filling plated layer 6a. The plated layer 6a serves as electrical interconnect lines 6.

Abstract translation: 一种制造光电混合基板的方法，其能够减少制造光电混合基板的步骤数量，并且能够实现要制造的光电混合基板的厚度的减小，以及光电 电动混合板。 以预定图案形成多个突出芯（光学互连线）3。 此后，在相邻的芯3之间的槽中形成薄金属膜4.通过填充电镀在金属薄膜4上，以填充电镀层6a填充上述槽。 镀层6a用作电互连线6。

公开(公告)号：US07586046B2

公开(公告)日：2009-09-08

申请号：US11514963

申请日：2006-09-05

Applicant: Jun Ishii ,  Yasuhito Funada ,  Yasunari Ooyabu

Inventor： Jun Ishii ,  Yasuhito Funada ,  Yasunari Ooyabu

IPC: H05K1/03

CPC classification number: H05K3/28 ,  H05K1/0259 ,  H05K1/056 ,  H05K1/167 ,  H05K3/16 ,  H05K2201/0769

Abstract: The invention provides a wired circuit board that can prevent deterioration of a conductive pattern and short-circuiting of the conductive pattern. The wired circuit board is presented herein in the form of a suspension board with circuit which comprises an insulating base layer formed on a metal supporting board, a conductive pattern formed on the insulating base layer, a metal oxide layer formed on a surface of the conductive pattern and on a surface of the insulating base layer by sputtering, and an insulating cover layer, formed on the metal oxide layer, to cover the conductive pattern. According to this suspension board with circuit, since the metal oxide layer to cover the conductive pattern is formed by the sputtering, the metal oxide layer can be formed with a uniform thickness. Hence, the metal oxide layer can fully function as a barrier layer to the conductive pattern and, accordingly, deterioration of the conductive pattern and the short-circuiting of the conductive pattern can be prevented effectively.

Abstract translation: 本发明提供一种布线电路板，其可以防止导电图案的劣化和导电图案的短路。 布线电路板在这里以具有电路的悬挂板的形式呈现，该电路包括形成在金属支撑板上的绝缘基底层，形成在绝缘基底层上的导电图案，形成在导电的表面上的金属氧化物层 通过溅射形成在绝缘基底层的表面上，以及形成在金属氧化物层上的覆盖导电图案的绝缘覆盖层。 根据具有电路的该悬挂板，由于通过溅射形成覆盖导电图案的金属氧化物层，所以可以形成均匀的厚度的金属氧化物层。 因此，金属氧化物层可以充分发挥导电图案的阻挡层的作用，因此可以有效地防止导电图案的劣化和导电图案的短路。

公开(公告)号：US20090190880A1

公开(公告)日：2009-07-30

申请号：US12358946

申请日：2009-01-23

Applicant: Takami HIKITA ,  Kazunori MUNE ,  Toshiki NAITOU ,  Yasunari OOYABU

Inventor： Takami HIKITA ,  Kazunori MUNE ,  Toshiki NAITOU ,  Yasunari OOYABU

IPC: G02B6/12 ,  B05D5/12

CPC classification number: G02B6/122 ,  G02B6/10 ,  G02B6/1221 ,  G02B6/13 ,  G02B6/132 ,  G02B6/136 ,  G02B6/43 ,  H05K1/0274 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/107 ,  H05K3/28 ,  H05K2203/0723

Abstract: A method of manufacturing an opto-electric hybrid board which is capable of reducing the number of steps for the manufacture of the opto-electric hybrid board and which achieves the reduction in thickness of the opto-electric hybrid board to be manufactured, and an opto-electric hybrid board obtained thereby. A plurality of protruding cores (optical interconnect lines) 3 are formed in a predetermined pattern. Thereafter, a thin metal film 4 is formed in grooves defined between adjacent ones of the cores 3. Via-filling plating is performed on the thin metal film 4 to fill the above-mentioned grooves with a via-filling plated layer 6a. The plated layer 6a serves as electrical interconnect lines 6.

Abstract translation: 一种制造光电混合基板的方法，其能够减少制造光电混合基板的步骤数量，并且能够实现要制造的光电混合基板的厚度的减小，以及光电 电动混合板。 以预定图案形成多个突出芯（光学互连线）3。 此后，在相邻的芯3之间形成的沟槽中形成薄金属薄膜4.在金属薄膜4上进行填充电镀，以填充上述沟槽。 镀层6a用作电互连线6。