公开(公告)号：US20090043926A1

公开(公告)日：2009-02-12

申请号：US12254575

申请日：2008-10-20

Applicant: Julie Hwang ,  Woo Jin Kim ,  Alan S. Bass ,  Mark W. Morgan

Inventor： Julie Hwang ,  Woo Jin Kim ,  Alan S. Bass ,  Mark W. Morgan

IPC: G06F3/00

CPC classification number: H03K19/0185

Abstract: A bidirectional repeater and data multiplexer for serial data has A-side 12C port devices A1-A4 coupled to comparators 302-308 and pull-downs to ground 316-322. Comparator outputs are coupled responsive to select lines S1-S4 of N:1 Select 310 to terminal A1 of bidirectional control 210 to control pull-down to non-zero low voltage Vp 206 at B-side device B. An inverting comparator 208 coupled to terminal B1 of bidirectional control 210 responds to input threshold voltage Vt less than low voltage Vp, to prevent data lockup due to data flowback to devices A1-A4. Output data from comparator 208 is coupled responsive to select lines S1-S4 of 1:N Select 312 to control pull-downs 316-322. This selectively repeats routing of device A1-A4 data to device B. Data from device B is selectively routed to pull-downs of devices A1-A4.

Abstract translation: 用于串行数据的双向中继器和数据多路复用器具有耦合到比较器302-308并且下拉到地316-322的A侧12C端口设备A1-A4。 比较器输出响应于N：1的选择线S1-S4选择310到双向控制210的端子A1，以控制在B侧装置B处的下拉至非零低电压Vp 206.反相比较器208耦合到 双向控制210的端子B1响应于小于低电压Vp的输入阈值电压Vt，以防止由于数据流回到设备A1-A4而导致的数据锁定。 响应于1：N选择312的选择线S1-S4来控制来自比较器208的输出数据以控制下拉316-322。 这选择性地重复设备A1-A4数据到设备B的路由。来自设备B的数据被选择性地路由到设备A1-A4的下拉。

公开(公告)号：US20070127300A1

公开(公告)日：2007-06-07

申请号：US11647398

申请日：2006-12-29

Applicant: Woo-Jin Kim ,  Kwang-Joon Park ,  Joo-Seok Kwak ,  Kwang-Won Lee ,  Jong-Jin Yi

Inventor： Woo-Jin Kim ,  Kwang-Joon Park ,  Joo-Seok Kwak ,  Kwang-Won Lee ,  Jong-Jin Yi

IPC: G11C29/00

CPC classification number: G11C29/12005 ,  G11C29/36

Abstract: A semiconductor memory device includes a switch circuit that inverts input data or output data when burn-in mode enable signals are activated or a control signal switch that inverts external control signals or internal control signals when burn-in mode enable signals are activated. A burn-in test method for the semiconductor memory device performs a pass/fail decision to determine whether the output data has passed or failed based on an inverted logical value of the input data.

Abstract translation: 半导体存储器件包括一个开关电路，当老化模式使能信号被激活时，其反相输入数据或输出数据，或者当老化模式使能信号被激活时转换外部控制信号或内部控制信号的控制信号开关。 半导体存储器件的老化测试方法基于输入数据的反相逻辑值执行通过/失败判定以确定输出数据是否通过或失败。

公开(公告)号：US20060128130A1

公开(公告)日：2006-06-15

申请号：US11003755

申请日：2004-12-02

Applicant: Se-Aug Jang ,  Heung-Jae Cho ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Seo-Min Kim ,  Tae-Woo Jung

Inventor： Se-Aug Jang ,  Heung-Jae Cho ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Seo-Min Kim ,  Tae-Woo Jung

IPC: H01L21/4763

CPC classification number: H01L29/66621 ,  H01L29/4236

Abstract: The present invention relates to a method for fabricating a recessed gate structure. The method includes the steps of: selectively etching a substrate to form a plurality of openings; forming a gate oxide layer on the openings and the substrate; forming a first conductive silicon layer on the gate oxide layer to form a plurality of valleys at a height equal to or greater than a thickness remaining after an intended pattern is formed; planarizing the first conductive silicon layer until the thickness remaining after the intended pattern formation is obtained, so that the valleys are removed; forming a second conductive layer on a planarized first conductive silicon layer; and selectively etching the second conductive layer, the first conductive silicon layer and the gate oxide layer to form a plurality of the recessed gate structures.

Abstract translation: 本发明涉及一种用于制造凹陷栅极结构的方法。 该方法包括以下步骤：选择性地蚀刻基板以形成多个开口; 在所述开口和所述基板上形成栅氧化层; 在所述栅极氧化层上形成第一导电硅层，以在形成预期图案之后的厚度等于或大于剩余的厚度上形成多个谷; 平面化第一导电硅层，直到获得预期图案形成之后剩余的厚度，从而除去谷; 在平坦化的第一导电硅层上形成第二导电层; 并且选择性地蚀刻第二导电层，第一导电硅层和栅极氧化物层以形成多个凹陷栅极结构。

公开(公告)号：US07045846B2

公开(公告)日：2006-05-16

申请号：US11053704

申请日：2005-02-07

Applicant: Se-Aug Jang ,  Tae-Woo Jung ,  Seo-Min Kim ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Young-Bog Kim ,  Hong-Seon Yang ,  Hyun-Chul Sohn ,  Eung-Rim Hwang

Inventor： Se-Aug Jang ,  Tae-Woo Jung ,  Seo-Min Kim ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Young-Bog Kim ,  Hong-Seon Yang ,  Hyun-Chul Sohn ,  Eung-Rim Hwang

IPC: H01L27/108

CPC classification number: H01L27/11521 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/115 ,  H01L29/7886

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract translation: 公开了一种存储器件及其制造方法。 存储器件包括：具有沟槽的衬底; 位于沟槽下面的位线接触结; 形成在沟槽外部的多个存储节点接触结; 以及多个栅极结构，每个栅极结构都形成在位于位线接触连接点与存储节点接触接点之一之间的衬底上。 沟槽的每个侧壁成为各个沟道的一部分，因此，单元区域中的晶体管的沟道长度变长。 因此，存储节点接触点具有降低的漏电流水平，从而增加数据保留时间。

公开(公告)号：US20060033684A1

公开(公告)日：2006-02-16

申请号：US11252405

申请日：2005-10-17

Applicant: Soo-Jin Lee ,  Woo-Jin Kim ,  Im-Su Choi

Inventor： Soo-Jin Lee ,  Woo-Jin Kim ,  Im-Su Choi

IPC: G09G3/28

CPC classification number: G09G3/2007 ,  G09G3/296 ,  G09G2320/0257 ,  G09G2320/0626 ,  G09G2360/16

Abstract: An after-image prevention apparatus and method for a plasma display panel having a plurality of address electrodes and a plurality of scan and sustain electrodes arranged in pairs and in a zigzag pattern. An average signal level until the current frame from currently input picture data and an average signal level of each cell until the previous frame as stored in a memory section is calculated. The average signal level is compared with the picture data. An attenuation coefficient is generated corresponding to the difference between the average signal level and the picture data. The picture data is multiplied by the attenuation coefficient to output correction data, thereby preventing an after-image phenomenon on the plasma display panel.

公开(公告)号：US06933759B1

公开(公告)日：2005-08-23

申请号：US10773554

申请日：2004-02-05

Applicant: Lin Wu ,  Robert Floyd Payne ,  Paul Eric Landman ,  Woo Jin Kim

Inventor： Lin Wu ,  Robert Floyd Payne ,  Paul Eric Landman ,  Woo Jin Kim

IPC: H03K3/017 ,  H03K5/151 ,  H03K5/156

CPC classification number: H03K5/151 ,  H03K5/1565

Abstract: The present invention facilitates serial communication by performing duty cycle correction. A duty cycle correction component 302 performs duty cycle corrections on a pair of differential sinusoidal signals according to a pair of adjustment signals and, as a result, generates a differential pair of square wave signals. A cross coupled buffer 306 buffers the differential pair of square wave signals and provides the buffered signals to a feedback circuit 304 that measures duty cycles of the signals and generates the pair of adjustment signals accordingly. The buffer 306 can also remove skew from the signals. In a transmitter 102, the buffered signals are also generally provided to a multiplexer 112 or encoder and in a receiver 106, the buffered signals are also generally provided to a sampling component 122.

Abstract translation: 本发明通过执行占空比校正来促进串行通信。 占空比校正部件302根据一对调整信号对一对差分正弦信号进行占空比校正，结果产生差分的方波信号。 交叉耦合缓冲器306缓冲差分对的方波信号，并将缓冲的信号提供给测量信号的占空比的反馈电路304，并相应地产生一对调整信号。 缓冲器306还可以消除信号的偏斜。 在发射机102中，经缓冲的信号也通常提供给多路复用器112或编码器，而在接收机106中，缓冲信号也通常提供给采样组件122。

公开(公告)号：US06342895B1

公开(公告)日：2002-01-29

申请号：US09221982

申请日：1998-12-29

Applicant: Woo-jin Kim

Inventor： Woo-jin Kim

IPC: G09G539

CPC classification number: H04N19/427 ,  H04N19/423 ,  H04N19/61

Abstract: A memory allocation method and apparatus is disclosed in which the macro blocks are grouped into a plurality block sets and stored in the memory as block set. By grouping and storing the macro blocks, an efficient reading of the data is achieved.

Abstract translation: 公开了一种存储器分配方法和装置，其中宏块被分组成多个块集合并作为块集存储在存储器中。 通过分组和存储宏块，实现数据的有效读取。

公开(公告)号：US5940413A

公开(公告)日：1999-08-17

申请号：US81030

申请日：1998-05-19

Applicant: Woo Jin Kim ,  Joo Suk Kwak ,  Kyung Wan Kim ,  Jeong Ho Bang

Inventor： Woo Jin Kim ,  Joo Suk Kwak ,  Kyung Wan Kim ,  Jeong Ho Bang

IPC: G01R31/26 ,  G01R31/01 ,  G01R31/319 ,  G11C29/56 ,  H01L21/66 ,  G11C29/00 ,  G01R31/28

CPC classification number: G01R31/01 ,  G01R31/31908

Abstract: A method for detecting operational errors in a tester of a test system for determining whether a semiconductor device is good or failed includes a diagnostic test having the step of periodically inputting data to the device and checking whether the data can be retrieved intact from the tester. If not, then an operational error may be present in the tester. The method requires that the diagnostic test be carried out after a predetermined number of devices has been tested, and that the data inputted to the device during the diagnostic test be inputted to every I/O pin of the device. The diagnostic test includes inputting a value of 0 to each I/O pin, and then comparing the output of the device to a predetermined expected value. The diagnostic test also includes inputting a value of 1 to each I/O pin, and similarly comparing the output to an expected value.

Abstract translation: 用于检测用于确定半导体器件是好还是失败的测试系统的测试器中的操作错误的方法包括具有周期性地向设备输入数据并检查数据是否能够从测试器完整检索的步骤的诊断测试。 否则，测试仪中可能会出现操作错误。 该方法要求在测试了预定数量的设备之后执行诊断测试，并且在诊断测试期间输入到设备的数据被输入到设备的每个I / O引脚。 诊断测试包括向每个I / O引脚输入值0，然后将器件的输出与预定的预期值进行比较。 诊断测试还包括为每个I / O引脚输入1值，并且类似地将输出与预期值进行比较。

公开(公告)号：US09224787B2

公开(公告)日：2015-12-29

申请号：US14193877

申请日：2014-02-28

Applicant: Whan-Kyun Kim ,  Young-Hyun Kim ,  Woo-Jin Kim

Inventor： Whan-Kyun Kim ,  Young-Hyun Kim ,  Woo-Jin Kim

IPC: H01L21/00 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L27/228 ,  H01L43/12

Abstract: A method for fabricating a nonvolatile memory device is provided. The method includes forming a transistor including an impurity region formed in a substrate, forming a first interlayer insulation layer covering the transistor, the first interlayer insulation layer including a protrusion overlapping the impurity region, and forming an information storage unit on the protrusion, the information storage unit exposing side surfaces of the protrusion using point cusp magnetron-physical vapor deposition (PCM-PVD) and electrically connected to the impurity region.

Abstract translation: 提供一种制造非易失性存储器件的方法。 该方法包括形成晶体管，其包括在衬底中形成的杂质区，形成覆盖晶体管的第一层间绝缘层，第一层间绝缘层包括与杂质区重叠的突起，以及在突起上形成信息存储单元， 存储单元使用尖点磁控管 - 物理气相沉积（PCM-PVD）暴露突起的侧表面并电连接到杂质区。

公开(公告)号：US09202742B1

公开(公告)日：2015-12-01

申请号：US14156271

申请日：2014-01-15

Applicant: Woo Jin Kim ,  Sun Jae Kim ,  Chung Lyul Ahn ,  Hyeon Yi Kang

Inventor： Woo Jin Kim ,  Sun Jae Kim ,  Chung Lyul Ahn ,  Hyeon Yi Kang

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L21/52 ,  H01L23/12 ,  H01L23/16

CPC classification number: H01L23/49827 ,  H01L21/52 ,  H01L21/56 ,  H01L21/563 ,  H01L23/12 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012

Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate; a device attached on a top surface of the substrate; a mold encapsulating the device, the mold having a through via and a recessed pattern characterized by being formed in a single process; and a conductive via in the through via and a conductive pattern in the recessed pattern characterized by being formed in another single process.

Abstract translation: 一种集成电路封装系统及其制造方法，包括：基板; 附着在所述基板的顶表面上的装置; 封装所述装置的模具，所述模具具有通孔和凹陷图案，其特征在于以单一工艺形成; 以及通孔中的导电通孔和凹陷图案中的导电图案，其特征在于在另一个单一工艺中形成。