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    Method for manufacturing semiconductor device
    2.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07560370B2

    公开(公告)日：2009-07-14

    申请号：US11618612

    申请日：2006-12-29

    Applicant: Seo Min Kim

    Inventor： Seo Min Kim

    IPC: H01L21/44 ,  H01L21/28 ,  H01L21/3205

    CPC classification number: H01L21/76895 ,  H01L27/1052

    Abstract: A method for forming a semiconductor device includes forming a bit line contact region with a line pattern and then performing a process to form a bit line so that a multi-layered bit line contact is expended, thereby preventing a short between bit line contact plugs and improving the process margin of semiconductor devices and the reliability of semiconductor devices.

    Abstract translation: 一种用于形成半导体器件的方法包括形成具有线图案的位线接触区域，然后执行形成位线的处理，从而消除多层位线接触，从而防止位线接触插头和 提高半导体器件的工艺裕度和半导体器件的可靠性。

    Method of Forming Pattern of Semiconductor Device
    3.
    发明申请
    Method of Forming Pattern of Semiconductor Device 失效
    半导体器件形成方法

    公开(公告)号：US20080286954A1

    公开(公告)日：2008-11-20

    申请号：US11947228

    申请日：2007-11-29

    Applicant: Seo Min Kim ,  Chang Moon Lim

    Inventor： Seo Min Kim ,  Chang Moon Lim

    IPC: H01L21/425

    CPC classification number: H01L21/32139 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  Y10S438/924

    Abstract: A method of forming a pattern of a semiconductor device comprises forming a first hard mask film, a first resist film, and a second hard mask film over an underlying layer of a semiconductor substrate; forming a second resist pattern over the second hard mask film; etching the second hard mask film using the second resist pattern as an etching mask to form a second hard mask pattern; performing an ion-implanting process on the first resist film with the second hard mask pattern as an ion implanting mask to form an ion implanting layer in a portion of the first resist film, and selectively etching the first resist film with the second hard mask pattern and an ion implanting layer as an etching mask to form a first resist pattern.

    Abstract translation: 形成半导体器件的图案的方法包括在半导体衬底的下层上形成第一硬掩模膜，第一抗蚀膜和第二硬掩模膜; 在所述第二硬掩模膜上形成第二抗蚀剂图案; 使用第二抗蚀剂图案作为蚀刻掩模蚀刻第二硬掩模膜以形成第二硬掩模图案; 对所述第一抗蚀剂膜进行离子注入工艺，其中所述第二硬掩模图案作为离子注入掩模，以在所述第一抗蚀剂膜的一部分中形成离子注入层，并且用所述第二硬掩模图案选择性地蚀刻所述第一抗蚀剂膜 以及作为蚀刻掩模的离子注入层以形成第一抗蚀剂图案。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
    制造半导体器件的方法

    公开(公告)号：US20070269971A1

    公开(公告)日：2007-11-22

    申请号：US11618612

    申请日：2006-12-29

    Applicant: Seo Min Kim

    Inventor： Seo Min Kim

    IPC: H01L21/44

    CPC classification number: H01L21/76895 ,  H01L27/1052

    Abstract: A method for forming a semiconductor device includes forming a bit line contact region with a line pattern and then performing a process to form a bit line so that a multi-layered bit line contact is expended, thereby preventing a short between bit line contact plugs and improving the process margin of semiconductor devices and the reliability of semiconductor devices.

    Abstract translation: 一种用于形成半导体器件的方法包括形成具有线图案的位线接触区域，然后执行形成位线的处理，以便消耗多层位线接触，从而防止位线接触插头和 提高半导体器件的工艺裕度和半导体器件的可靠性。

    Method for fabricating recessed gate structure
    5.
    发明申请
    Method for fabricating recessed gate structure 审中-公开
    凹陷门结构的制造方法

    公开(公告)号：US20060128130A1

    公开(公告)日：2006-06-15

    申请号：US11003755

    申请日：2004-12-02

    Applicant: Se-Aug Jang ,  Heung-Jae Cho ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Seo-Min Kim ,  Tae-Woo Jung

    Inventor： Se-Aug Jang ,  Heung-Jae Cho ,  Woo-Jin Kim ,  Hyung-Soon Park ,  Seo-Min Kim ,  Tae-Woo Jung

    IPC: H01L21/4763

    CPC classification number: H01L29/66621 ,  H01L29/4236

    Abstract: The present invention relates to a method for fabricating a recessed gate structure. The method includes the steps of: selectively etching a substrate to form a plurality of openings; forming a gate oxide layer on the openings and the substrate; forming a first conductive silicon layer on the gate oxide layer to form a plurality of valleys at a height equal to or greater than a thickness remaining after an intended pattern is formed; planarizing the first conductive silicon layer until the thickness remaining after the intended pattern formation is obtained, so that the valleys are removed; forming a second conductive layer on a planarized first conductive silicon layer; and selectively etching the second conductive layer, the first conductive silicon layer and the gate oxide layer to form a plurality of the recessed gate structures.

    Abstract translation: 本发明涉及一种用于制造凹陷栅极结构的方法。 该方法包括以下步骤：选择性地蚀刻基板以形成多个开口; 在所述开口和所述基板上形成栅氧化层; 在所述栅极氧化层上形成第一导电硅层，以在形成预期图案之后的厚度等于或大于剩余的厚度上形成多个谷; 平面化第一导电硅层，直到获得预期图案形成之后剩余的厚度，从而除去谷; 在平坦化的第一导电硅层上形成第二导电层; 并且选择性地蚀刻第二导电层，第一导电硅层和栅极氧化物层以形成多个凹陷栅极结构。

    Semiconductor memory device and method for fabricating the same
    7.
    发明授权
    Semiconductor memory device and method for fabricating the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US07012002B2

    公开(公告)日：2006-03-14

    申请号：US10749750

    申请日：2003-12-30

    Applicant: Seo-Min Kim ,  Cheol-Kyu Bok

    Inventor： Seo-Min Kim ,  Cheol-Kyu Bok

    IPC: H01L21/8242

    CPC classification number: H01L27/10855 ,  H01L21/768 ,  H01L27/101 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor memory device and a method for fabricating the same. Particularly, the semiconductor memory device includes at least two capacitors to decrease the thickness of an insulation layer and increase the size of each capacitor, wherein the thickness of the insulation layer and the size of the capacitor are factors for increasing parasitic capacitance and leakage currents. Also, the two capacitors are arranged diagonally, thereby widening the width of each capacitor formed. Furthermore, in forming double capacitors according to the preferred embodiment of the present invention, an additional reticle is not required to form the contact holes for each capacitor due to their inverted disposition relationship.

    Abstract translation: 一种半导体存储器件及其制造方法。 特别地，半导体存储器件包括至少两个电容器以减小绝缘层的厚度并增加每个电容器的尺寸，其中绝缘层的厚度和电容器的尺寸是增加寄生电容和漏电流的因素。 此外，两个电容器对角布置，从而加宽形成的每个电容器的宽度。 此外，在根据本发明的优选实施例的形成双电容器中，由于它们的倒置配置关系，不需要额外的掩模版来形成每个电容器的接触孔。

    EXPOSURE MASK WITH DOUBLE PATTERNING TECHNOLOGY AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME
    8.
    发明申请
    EXPOSURE MASK WITH DOUBLE PATTERNING TECHNOLOGY AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME 失效
    具有双重绘图技术的曝光掩模和使用其制造半导体器件的方法

    公开(公告)号：US20110275014A1

    公开(公告)日：2011-11-10

    申请号：US13186723

    申请日：2011-07-20

    Applicant: Seo Min KIM

    Inventor： Seo Min KIM

    IPC: G03F1/14

    CPC classification number: G03F1/00

    Abstract: An exposure mask for forming a G-type active region with a double patterning technology includes a bar shaped first light-blocking pattern to define an I-type active region, and an island shaped second light-blocking pattern to define a bit line contact region. The first light-blocking pattern and the second light-blocking pattern are arranged alternately.

    Abstract translation: 用于通过双重图案形成技术形成G型有源区的曝光掩模包括用于限定I型有源区的棒状第一遮光图案和用于限定位线接触区域的岛状第二遮光图案 。 第一遮光图案和第二遮光图案交替布置。

    Method of forming pattern of semiconductor device
    9.
    发明授权
    Method of forming pattern of semiconductor device 失效
    半导体器件形成方法

    公开(公告)号：US07553771B2

    公开(公告)日：2009-06-30

    申请号：US11947228

    申请日：2007-11-29

    Applicant: Seo Min Kim ,  Chang Moon Lim

    Inventor： Seo Min Kim ,  Chang Moon Lim

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/32139 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  Y10S438/924

    Abstract: A method of forming a pattern of a semiconductor device comprises forming a first hard mask film, a first resist film, and a second hard mask film over an underlying layer of a semiconductor substrate; forming a second resist pattern over the second hard mask film; etching the second hard mask film using the second resist pattern as an etching mask to form a second hard mask pattern; performing an ion-implanting process on the first resist film with the second hard mask pattern as an ion implanting mask to form an ion implanting layer in a portion of the first resist film, and selectively etching the first resist film with the second hard mask pattern and an ion implanting layer as an etching mask to form a first resist pattern.

    Abstract translation: 形成半导体器件的图案的方法包括在半导体衬底的下层上形成第一硬掩模膜，第一抗蚀膜和第二硬掩模膜; 在所述第二硬掩模膜上形成第二抗蚀剂图案; 使用第二抗蚀剂图案作为蚀刻掩模蚀刻第二硬掩模膜以形成第二硬掩模图案; 对所述第一抗蚀剂膜进行离子注入处理，其中所述第二硬掩模图案作为离子注入掩模，以在所述第一抗蚀剂膜的一部分中形成离子注入层，并且用所述第二硬掩模图案选择性地蚀刻所述第一抗蚀剂膜 以及作为蚀刻掩模的离子注入层以形成第一抗蚀剂图案。

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