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126 条记录 (耗时 0.025 秒)

    Non-volatile semiconductor memory device and data programming method
    41.
    发明授权
    Non-volatile semiconductor memory device and data programming method 失效
    非易失性半导体存储器件和数据编程方法

    公开(公告)号：US06344999B1

    公开(公告)日：2002-02-05

    申请号：US09677902

    申请日：2000-10-03

    申请人： Hiroshi Iwahashi

    发明人： Hiroshi Iwahashi

    IPC分类号： G11C1604

    CPC分类号： G11C16/12 ,  G11C16/0483

    摘要： In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored much in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

    摘要翻译： 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均以减小其阈值电压的偏差。 来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任何一个存储在存储器单元组或块的存储单元中，将负阈值电压分配给用于存储更多位侧的存储单元 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，数据锁存电路可以形成在远离存储单元阵列的任何位置处。

    Nonvolatile semiconductor memory
    42.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US06292423B1

    公开(公告)日：2001-09-18

    申请号：US09605423

    申请日：2000-06-28

    申请人： Hiroshi Iwahashi

    发明人： Hiroshi Iwahashi

    IPC分类号： G11C700

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/08 ,  G11C2211/5642

    摘要： A nonvolatile semiconductor memory is disclosed. This nonvolatile semiconductor memory includes a memory cell string containing a selection transistor and at least one cell transistor which is connected to the selection transistor and has a floating gate. This memory further includes a bias circuit for, when the selection transistor is unselected, supplying a potential different from the ground potential to the gate of the cell transistor connected to the unselected selection transistor.

    摘要翻译： 公开了一种非易失性半导体存储器。 该非易失性半导体存储器包括一个包含选择晶体管的存储单元串和至少一个与选择晶体管相连并具有浮置栅极的单元晶体管。 该存储器还包括偏置电路，用于当选择晶体管未被选择时，向与未选择的选择晶体管连接的单元晶体管的栅极提供不同于地电位的电位。

    Memory cell of non-volatile semiconductor memory device
    44.
    发明授权
    Memory cell of non-volatile semiconductor memory device 失效
    非易失性半导体存储器件的存储单元

    公开(公告)号：US6058051A

    公开(公告)日：2000-05-02

    申请号：US901660

    申请日：1997-07-28

    申请人： Hiroshi Iwahashi

    发明人： Hiroshi Iwahashi

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C7/00

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

    摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

    摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 该串联电路一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。

    Semiconductor memory device including circuitry for selecting a block in both read and write modes
    45.
    发明授权
    Semiconductor memory device including circuitry for selecting a block in both read and write modes 失效
    半导体存储器件包括用于在读取和写入模式中选择块的电路

    公开(公告)号：US5877982A

    公开(公告)日：1999-03-02

    申请号：US848227

    申请日：1997-04-29

    申请人： Hiroshi Iwahashi

    发明人： Hiroshi Iwahashi

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

    摘要： The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

    摘要翻译： 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 该串联电路一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。

    Semiconductor integrated circuit protected from element breakdown by reducing the electric field between the gate and drain or source of a field effect transistor
    48.
    发明授权
    Semiconductor integrated circuit protected from element breakdown by reducing the electric field between the gate and drain or source of a field effect transistor 失效
    半导体集成电路通过减小场效应晶体管的栅极和漏极或源极之间的电场来保护元件击穿

    公开(公告)号：US5336952A

    公开(公告)日：1994-08-09

    申请号：US67102

    申请日：1993-05-26

    申请人： Hiroshi Iwahashi ,  Toshiyuki Fujimoto ,  Akira Narita

    发明人： Hiroshi Iwahashi ,  Toshiyuki Fujimoto ,  Akira Narita

    IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/12 ,  H03K17/10 ,  H03K17/687

    CPC分类号： G11C5/145 ,  G11C16/12 ,  G11C8/08 ,  H03K17/102

    摘要： A semiconductor integrated circuit which is protected from element breakdown includes a memory cell, series-connected first and second program load transistors arranged between the memory cell and the program power source, a boosting circuit for outputting a board voltage higher than the voltage of a program power source, and a controller. The controller applies the boosted voltage to the gates of the first and second program load transistors when program data is set at a first logic level. The controller applies a voltage of about 0 V to the gate of the first program load transistor and an intermediate voltage lower than the voltage of the program power source and higher than 0 V to the gate of the second load transistor when the program data is set at a second logic level.

    摘要翻译： 防止元件击穿的半导体集成电路包括布置在存储单元和编程电源之间的存储单元，串联连接的第一和第二程序负载晶体管，用于输出高于程序电压的电路板电压的升压电路 电源和控制器。 当程序数据被设置在第一逻辑电平时，控制器将升压电压施加到第一和第二编程负载晶体管的栅极。 当程序数据被设置时，控制器向第一编程负载晶体管的栅极施加大约0V的电压和低于编程电源电压的中间电压并且高于0V到第二负载晶体管的栅极 在第二逻辑级别。

    Semiconductor integrated circuit
    49.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US5214609A

    公开(公告)日：1993-05-25

    申请号：US751768

    申请日：1991-08-29

    申请人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Nobuaki Hiraga

    发明人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Nobuaki Hiraga

    IPC分类号： G11C11/41 ,  G11C7/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/18 ,  G11C11/407 ,  G11C11/409 ,  G11C16/06

    CPC分类号： G11C7/02 ,  G11C7/062 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C8/18

    摘要： In the semiconductor integrated circuit, the data delay circuit and data latch circuit are connected between the sense amplifier circuit and the output buffer circuit. A pulse signal for controlling the output buffer is first generated according to a pulse output signal of the address change detection circuit, and then a latch signal which permits output data of the data detection circuit obtained before the change of the address input signal to be latched by the data latch circuit for a preset period of time is generated. Next, a delay signal is generated which sets the delay time of the data delay circuit to be short in a case where data detected by the data detection circuit is not output from the output buffer circuit, and sets the delay time of the data delay circuit to be long in a case where data is output from the output buffer circuit. Generation of the delay signal is interrupted after the pulse signal of the address change detection circuit is interrupted. As a result, the power source variation at the time of output data change or erroneous operation due to noise input from the exterior can be prevented. Further, the driving ability of the output buffer transistor can be set to a large value so that a highly reliable semiconductor integrated circuit in which the operation margin of the integrated circuit with respect to the power source variation and noise can be made large while keeping the data readout speed high can be obtained.