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109 条记录 (耗时 0.026 秒)

    High-voltage vertical transistor with a multi-gradient drain doping profile
    41.
    发明授权
    High-voltage vertical transistor with a multi-gradient drain doping profile 失效
    具有多梯度漏极掺杂特性的高压垂直晶体管

    公开(公告)号：US07335944B2

    公开(公告)日：2008-02-26

    申请号：US11699936

    申请日：2007-01-30

    申请人： Sujit Banerjee ,  Donald Ray Disney

    发明人： Sujit Banerjee ,  Donald Ray Disney

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7802 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  Y10S438/925

    摘要： A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 高压晶体管包括在半导体衬底中限定台面的第一和第二沟槽。 第一和第二场板构件分别设置在第一和第二沟槽中，第一和第二场板构件中的每一个通过介电层与台面分离。 台面包括多个部分，每个部分具有基本上恒定的掺杂浓度梯度，一个部分的梯度比另一部分的梯度大至少10％。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    ESD protection for bipolar-CMOS-DMOS integrated circuit devices and modular method of forming the same
    42.
    发明申请
    ESD protection for bipolar-CMOS-DMOS integrated circuit devices and modular method of forming the same 有权
    双极CMOS-DMOS集成电路器件的ESD保护及其形成的模块化方法

    公开(公告)号：US20080029820A1

    公开(公告)日：2008-02-07

    申请号：US11499381

    申请日：2006-08-04

    申请人： Donald Ray Disney ,  Jun-Wei Chen ,  Richard K. Williams ,  HyungSik Ryu ,  Wai Tien Chan

    发明人： Donald Ray Disney ,  Jun-Wei Chen ,  Richard K. Williams ,  HyungSik Ryu ,  Wai Tien Chan

    IPC分类号： H01L23/62

    CPC分类号： H01L29/735 ,  H01L27/0251 ,  H01L29/0626 ,  H01L29/0692 ,  H01L29/7317 ,  H01L29/7833 ,  H01L29/861 ,  H01L29/866

    摘要： An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

    摘要翻译： 在半导体衬底的隔离区域中形成静电放电（ESD）保护器件。 ESD保护器件可以是MOS或双极晶体管或二极管的形式。 隔离结构可以包括深度植入的地板层和横向围绕隔离区域的一个或多个植入的孔。 隔离结构和ESD保护器件使用模块化工艺制造，其中几乎不包括热处理。 由于ESD器件是隔离的，所以两个或多个ESD器件可以彼此电“堆叠”，使得器件的触发电压相加在一起以实现更高的有效触发电压。

    High-voltage lateral transistor with a multi-layered extended drain structure
    45.
    发明授权
    High-voltage lateral transistor with a multi-layered extended drain structure 失效
    具有多层延伸漏极结构的高压横向晶体管

    公开(公告)号：US06798020B2

    公开(公告)日：2004-09-28

    申请号：US10361377

    申请日：2003-02-10

    申请人： Donald Ray Disney ,  Mohamed Darwish

    发明人： Donald Ray Disney ,  Mohamed Darwish

    IPC分类号： H01L2976

    CPC分类号： H01L29/7802 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/86 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

    摘要翻译： 具有低特定导通电阻并且支持处于截止状态的高电压的高电压晶体管包括邻近多层延伸漏极结构设置的一个或多个源极区域，其包括通过 一个或多个电介质层。 在场板成员处于最低电路电位的情况下，晶体管支持在截止状态下施加到漏极的高电压。 层状结构可以以各种取向制造。 可以将MOSFET结构并入到与源极区域相邻的器件中，或者，可以省略MOSFET结构以产生具有独立漂移区域的高压晶体管结构。

    Method of fabricating high-voltage transistor with buried conduction layer
    46.
    发明授权
    Method of fabricating high-voltage transistor with buried conduction layer 失效
    制造具有埋入导电层的高压晶体管的方法

    公开(公告)号：US06730585B2

    公开(公告)日：2004-05-04

    申请号：US10392622

    申请日：2003-03-20

    申请人： Donald Ray Disney

    发明人： Donald Ray Disney

    IPC分类号： H01L2122

    CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

    摘要： Method of fabricating a lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

    摘要翻译： 制造具有低导通电阻和掩埋导电层的横向高压FET的方法包括在P型衬底中形成的N阱内的P型掩埋层区域。 P型掩埋层区域通过设置在N阱区域中的第一P型漏极扩散区域与漏电极连接。 P型掩埋层区域也连接到从PMOS栅极区域的一端的表面向下延伸的第二P型漏极扩散区域。 连接到源电极的P型源极扩散区限定栅极区域的另一端。

    High-voltage transistor with buried conduction layer
    48.
    发明授权
    High-voltage transistor with buried conduction layer 有权
    具有埋电导层的高压晶体管

    公开(公告)号：US06501130B2

    公开(公告)日：2002-12-31

    申请号：US10176345

    申请日：2002-06-20

    申请人： Donald Ray Disney

    发明人： Donald Ray Disney

    IPC分类号： H01L31062

    CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835

    摘要： A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

    摘要翻译： 具有低导通电阻和掩埋导电层的横向高电压FET包括在P型衬底中形成的N阱内的P型掩埋层区域。 P型掩埋层区域通过设置在N阱区域中的第一P型漏极扩散区域与漏电极连接。 P型掩埋层区域也连接到从PMOS栅极区域的一端的表面向下延伸的第二P型漏极扩散区域。 连接到源电极的P型源极扩散区限定栅极区域的另一端。

    Method of making a insulated gate bipolar transistor with high-energy P+ implant and silicon-etch contact
    49.
    发明授权
    Method of making a insulated gate bipolar transistor with high-energy P+ implant and silicon-etch contact 失效
    制造具有高能P +注入和硅蚀刻接触的绝缘栅双极晶体管的方法

    公开(公告)号：US5910668A

    公开(公告)日：1999-06-08

    申请号：US909436

    申请日：1997-06-09

    申请人： Donald Ray Disney

    发明人： Donald Ray Disney

    IPC分类号： H01L21/331 ,  H01L29/739 ,  H01L29/76 ,  H01L29/74

    CPC分类号： H01L29/6634 ,  H01L29/7396

    摘要： An improved insulated gate bipolar transistor (IGBT) device structure and a method for fabricating such a device. This structure uses self-aligned and substantially undiffused successive N+ and P+ implants. The P+ implant is at high energy, which forms a subsurface P+ region below the entire bottom of an N+ "source" region of the IGBT. This low resistivity region suppresses thyristor latch-up when contacted via a surface trench. Self-aligned techniques provide method and product improvements.

    摘要翻译： 一种改进的绝缘栅双极晶体管（IGBT）器件结构及其制造方法。 这种结构使用自对准和基本上不扩散的连续N +和P +植入物。 P +植入物处于高能量，在IGBT的N +“源极”区域的整个底部下方形成地下P +区域。 该低电阻率区域通过表面沟槽接触时抑制晶闸管闭锁。 自对准技术提供了方法和产品改进。