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    DATA REORGANIZATION IN NON-UNIFORM CACHE ACCESS CACHES
    41.
    发明申请
    DATA REORGANIZATION IN NON-UNIFORM CACHE ACCESS CACHES 有权
    非均匀缓存访问缓存中的数据重组

    公开(公告)号：US20100274973A1

    公开(公告)日：2010-10-28

    申请号：US12429754

    申请日：2009-04-24

    申请人： Ganesh Balakrishnan ,  Gordon B. Bell ,  Anil Krishna ,  Srinivasan Ramani

    发明人： Ganesh Balakrishnan ,  Gordon B. Bell ,  Anil Krishna ,  Srinivasan Ramani

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0846 ,  G06F12/0811

    摘要： Embodiments that dynamically reorganize data of cache lines in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are horizontally distributed across multiple banks. To improve access latency of the data by the processors, the computing devices may dynamically propagate cache lines into banks closer to the processors using the cache lines. To accomplish such dynamic reorganization, embodiments may maintain “direction” bits for cache lines. The direction bits may indicate to which processor the data should be moved. Further, embodiments may use the direction bits to make cache line movement decisions.

    摘要翻译： 预期在非均匀缓存访问（NUCA）高速缓存中动态地重组高速缓存线的数据的实施例。 各种实施例包括具有与一个或多个NUCA高速缓存元件耦合的一个或多个处理器的计算设备。 NUCA高速缓存元件可以包括一个或多个高速缓冲存储器组，其中高速缓存的方式在多个存储体之间水平分布。 为了改善处理器对数据的访问等待时间，计算设备可以使用高速缓存行来将缓存线路动态地传播到更靠近处理器的存储体中。 为了实现这种动态重组，实施例可以保持高速缓存行的“方向”位。 方向位可以指示哪个处理器应该移动数据。 此外，实施例可以使用方向位来进行高速缓存行移动决定。

    DYNAMIC OPTIMIZATION OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTROLLER PAGE POLICY
    42.
    发明申请
    DYNAMIC OPTIMIZATION OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTROLLER PAGE POLICY 审中-公开
    动态随机存取存储器（DRAM）控制器页面策略动态优化

    公开(公告)号：US20080282028A1

    公开(公告)日：2008-11-13

    申请号：US11746411

    申请日：2007-05-09

    申请人： Ganesh Balakrishnan ,  Anil Krishna

    发明人： Ganesh Balakrishnan ,  Anil Krishna

    IPC分类号： G06F12/00

    CPC分类号： G11C11/4076 ,  G06F12/0215 ,  G06F2212/1016 ,  G06F2212/6026 ,  G11C7/1045 ,  G11C11/4072

    摘要： Embodiments of the present invention address deficiencies of the art in respect to memory management and provide a method, system and computer program product for dynamic optimization of DRAM controller page policy. In one embodiment of the invention, a memory module can include multiple different memories, each including a memory controller coupled to a memory array of memory pages. Each of the memory pages in turn can include a corresponding locality tendency state. A memory bank can be coupled to a sense amplifier and configured to latch selected ones of the memory pages responsive to the memory controller. Finally, the module can include open page policy management logic coupled to the memory controller. The logic can include program code enabled to granularly change open page policy management of the memory bank responsive to identifying a locality tendency state for a page loaded in the memory bank.

    摘要翻译： 本发明的实施例解决了存储器管理方面的缺陷，并且提供了用于DRAM控制器页面策略的动态优化的方法，系统和计算机程序产品。 在本发明的一个实施例中，存储器模块可以包括多个不同的存储器，每个存储器包括耦合到存储器页的存储器阵列的存储器控​​制器。 每个存储器页面又可以包括相应的局部趋势状态。 存储器组可以耦合到读出放大器并被配置为响应于存储器控制器来锁存存储器页中的选定存储器页。 最后，模块可以包括耦合到存储器控制器的开放页面策略管理逻辑。 该逻辑可以包括能够响应于识别加载在存储体中的页面的位置倾向状态，使得能够精细地改变存储体的打开页面策略管理的程序代码。

    PREVIOUSLY AIRED EPISODE RETRIEVAL BASED ON SERIES DVR SCHEDULING
    44.
    发明申请
    PREVIOUSLY AIRED EPISODE RETRIEVAL BASED ON SERIES DVR SCHEDULING 有权
    基于系列DVR调度的先前空气回波检测

    公开(公告)号：US20130283317A1

    公开(公告)日：2013-10-24

    申请号：US13453105

    申请日：2012-04-23

    申请人： Anil Krishna Guntupalli ,  Sameer Vasant Gavade ,  Shafiq Kassam ,  Venkata S. Adimatyam

    发明人： Anil Krishna Guntupalli ,  Sameer Vasant Gavade ,  Shafiq Kassam ,  Venkata S. Adimatyam

    IPC分类号： H04N21/462

    CPC分类号： H04N21/4147 ,  H04N21/4334 ,  H04N21/4622 ,  H04N21/47202 ,  H04N21/47214 ,  H04N21/4828 ,  H04N21/84

    摘要： A device receives an identification of a series to schedule automatic recording of episodes that are currently airing or that will be airing in the future, receives an instruction to automatically retrieve previously aired episodes of the scheduled series based on the scheduling of the automatic recording of the episodes that are currently airing or that will be airing in the future. The device searches content, based on receipt of the instruction, to retrieve previously aired episodes of the scheduled series. The device records at least one episode of the scheduled series, and presents the recorded at least one episode of the scheduled series and the previously aired episodes of the scheduled series such that a user may select and play the at least one episode of the scheduled series or the previously aired episodes of the scheduled series.

    摘要翻译： 一个装置接收一系列的标识，以便安排自动记录当前播放或将来播放的情节，接收一个指令，以便根据自动记录的调度自动检索预定序列的先前播出的剧集 目前正在播出或将来播出的剧集。 该设备根据该指令的接收来搜索内容以检索预定系列的以前播放的剧集。 所述设备记录所述预定系列的至少一个剧集，并且呈现所述预定系列的所记录的至少一个剧集和所述预定系列的先前播放的剧集，使得用户可以选择并播放所述预定系列的至少一个剧集 或预定系列的以前播出的剧集。

    Prefetching with multiple processors and threads via a coherency bus
    45.
    发明授权
    Prefetching with multiple processors and threads via a coherency bus 失效
    通过一个一致性总线预取多个处理器和线程

    公开(公告)号：US08543767B2

    公开(公告)日：2013-09-24

    申请号：US13488215

    申请日：2012-06-04

    申请人： Gordon B. Bell ,  Gordon T. Davis ,  Jeffrey H. Derby ,  Anil Krishna ,  Srinivasan Ramani ,  Ken Vu ,  Steve Woolet

    发明人： Gordon B. Bell ,  Gordon T. Davis ,  Jeffrey H. Derby ,  Anil Krishna ,  Srinivasan Ramani ,  Ken Vu ,  Steve Woolet

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0862 ,  G06F12/0831 ,  G06F2212/6026

    摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.

    摘要翻译： 处理系统包括被配置为处理应用的存储器和第一核心。 第一个核心包括第一个缓存。 处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。 所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。 第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

    REINFORCING BAR AND METHOD FOR MANUFACTURING THE SAME
    46.
    发明申请
    REINFORCING BAR AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    增强棒及其制造方法

    公开(公告)号：US20120328896A1

    公开(公告)日：2012-12-27

    申请号：US13582425

    申请日：2011-02-22

    申请人： Anil Krishna Kar

    发明人： Anil Krishna Kar

    IPC分类号： E04C5/06 ,  C21D8/00 ,  B21H7/00

    CPC分类号： E04C5/01 ,  E04C5/03 ,  Y10T428/12

    摘要： An improved reinforcing bar (REBAR) and the process for manufacturing the same for the enhancement of the life span of reinforced concrete, reinforced concrete structures and constructions as well as reinforced concrete elements without the need for any surface treatment or surface protection to REBAR or addition of admixture in concrete or without any other special provision or effort following the making/manufacturing of REBAR where the rebar, even when made of high strength steel or any other material, has a plain surface but with a deformed axis for use in all concrete constructions. The improved reinforcing bar (REBAR) for reinforced concrete constructions and reinforced concrete structures comprising a high strength material, a circular or oval or elliptical cross section of said bar; deformation of the axis of the bar in specific plane(s).

    摘要翻译： 改进的钢筋（REBAR）及其制造方法，用于增强钢筋混凝土，钢筋混凝土结构和结构以及钢筋混凝土构件的使用寿命，而无需对REBAR或添加物进行任何表面处理或表面保护 混凝土中的混合物或在制造/制造REBAR后没有任何其他特殊规定或努力，其中钢筋即使由高强度钢或任何其他材料制成，具有平坦表面但具有用于所有混凝土结构的变形轴 。 用于钢筋混凝土结构的改进的钢筋（REBAR）和钢筋混凝土结构，包括高强度材料，所述杆的圆形或椭圆形或椭圆形横截面; 杆在特定平面中的轴线的变形。

    EFFECTIVE PREFETCHING WITH MULTIPLE PROCESSORS AND THREADS
    47.
    发明申请
    EFFECTIVE PREFETCHING WITH MULTIPLE PROCESSORS AND THREADS 失效
    有效的预处理与多个处理器和螺纹

    公开(公告)号：US20120246406A1

    公开(公告)日：2012-09-27

    申请号：US13488215

    申请日：2012-06-04

    申请人： Gordon Bernard Bell ,  Gordon Taylor Davis ,  Jeffrey Haskell Derby ,  Anil Krishna ,  Srinivasan Ramani ,  Ken Vu ,  Steve Woolet

    发明人： Gordon Bernard Bell ,  Gordon Taylor Davis ,  Jeffrey Haskell Derby ,  Anil Krishna ,  Srinivasan Ramani ,  Ken Vu ,  Steve Woolet

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F12/0831 ,  G06F2212/6026

    摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.

    摘要翻译： 处理系统包括被配置为处理应用的存储器和第一核心。 第一个核心包括第一个缓存。 处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。 所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。 第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

    Cache architecture with distributed state bits
    49.
    发明授权
    Cache architecture with distributed state bits 有权
    具有分布状态位的缓存结构

    公开(公告)号：US08171220B2

    公开(公告)日：2012-05-01

    申请号：US12429586

    申请日：2009-04-24

    申请人： Ganesh Balakrishnan ,  Anil Krishna

    发明人： Ganesh Balakrishnan ,  Anil Krishna

    IPC分类号： G06F12/00

    CPC分类号： G06F12/126 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0817 ,  G06F12/0864 ,  Y02D10/13 ,  Y02D10/14

    摘要： Embodiments that that distribute replacement policy bits and operate the bits in cache memories, such as non-uniform cache access (NUCA) caches, are contemplated. An embodiment may comprise a computing device, such as a computer having multiple processors or multiple cores, which has cache memory elements coupled with the multiple processors or cores. The cache memory device may track usage of cache lines by using a number of bits. For example, a controller of the cache memory may manipulate bits as part of a pseudo least recently used (LRU) system. Some of the bits may be in a centralized area of the cache. Other bits of the pseudo LRU system may be distributed across the cache. Distributing the bits across the cache may enable the system to conserve additional power by turning off the distributed bits.

    摘要翻译： 考虑分配替换策略位并在高速缓冲存储器中操作诸如非均匀高速缓存存取（NUCA）高速缓存的位的实施例。 实施例可以包括计算设备，诸如具有多个处理器或多个核心的计算机，其具有与多个处理器或核心耦合的高速缓存存储器元件。 高速缓冲存储器设备可以通过使用多个位来跟踪高速缓存行的使用。 例如，高速缓冲存储器的控制器可以操作位作为伪最近最少使用（LRU）系统的一部分。 一些位可能在缓存的集中区域中。 伪LRU系统的其他位可以分布在高速缓存中。 通过高速缓存分配这些位可以使系统通过关闭分布式位来节省额外的功率。