公开(公告)号：US3789359A

公开(公告)日：1974-01-29

申请号：US3789359D

申请日：1972-10-04

Applicant: HARRIS INTERTYPE CORP

Inventor： CLARK G ,  DAVIS R

IPC: H03M13/33 ,  H04L1/00 ,  G08C25/00 ,  H04L1/10

CPC classification number: H04L1/0059 ,  H03M13/33

Abstract: Apparatus for synchronizing a decoder of convolution codes with a received stream of convolutional code data. Synchronization is achieved with respect to such problems as bit polarity inversion and incorrect boundaries of branch intervals by examining a number of trial message sequences. The trial message sequences are obtained by an algorithm suggested by Viterbi involving selection of one survivor sequence terminating in each data state of the code. When the decoder is synchronized with the received data stream, the survivor data sequences are very probably all identical at a branch interval near the older-data end of the sequences. When the decoder is not synchronized, the survivor sequences, with high probability, differ from each other at that branch interval. Loss of synchronism is detected by simultaneously examining the survivor sequences at a branch interval located at a selected number L of branch intervals before the last-received data, L being less than or equal to the decoding depth. If the survivor sequences are not unanimous at depth L a count is registered. If the number of such counts occurring within a test period of B successive branch intervals exceeds a predetermined threshold T, branch synchronism is presumed to be incorrect and a search is initiated for correct synchronism.

Abstract translation: 用于使卷积码的解码器与接收的卷积码数据流同步的装置。 通过检查多个试用消息序列，实现了比特极性反转和分支间隔边界错误等问题的同步。 试验消息序列通过由维特比建议的算法获得，涉及选择终止于代码的每个数据状态的一个幸存者序列。 当解码器与接收到的数据流同步时，幸存者数据序列在序列的较旧数据端附近的分支间隔可能全部相同。 当解码器不同步时，具有高概率的幸存者序列在该分支间隔处彼此不同。 通过在位于最后接收数据之前的分支间隔的选定数量L的分支间隔处同时检查幸存者序列，L小于或等于解码深度来检测同步丢失。 如果幸存者序列在深度L上不一致，则记录计数。 如果在B个连续分支间隔的测试周期内发生的这种计数的数量超过预定阈值T，则假定分支同步不正确，并且启动搜索以进行正确的同步。

公开(公告)号：US3668632A

公开(公告)日：1972-06-06

申请号：US3668632D

申请日：1969-02-13

Applicant: IBM

Inventor： OLDHAM IRA B

IPC: G06F11/10 ,  H04L1/10

CPC classification number: G06F11/1076 ,  G06F11/1008

Abstract: Apparatus for detecting and correcting errors in a digital computer storage system is disclosed. Data is encoded using a generalized Reed-Solomon encoder. Error detection circuitry including power sum calculating devices are used for detection of data in error. The error correction portion of the invention includes an improved decoding scheme for determining the location and magnitudes of errors within the data and has a very low average correction time. Means are provided for determining the starting area of a data block in the presence of errors in the starting area. Further means are provided for detecting a cyclic shift in a data character which, under normal conditions, would appear as an acceptable code word even though in error.

Abstract translation: 公开了一种用于检测和校正数字计算机存储系统中的错误的装置。 使用广义Reed-Solomon编码器对数据进行编码。 包括功率和计算装置的误差检测电路用于检测错误的数据。 本发明的纠错部分包括用于确定数据内的误差的位置和幅度的改进的解码方案，并且具有非常低的平均校正时间。 提供用于在起始区域中存在错误的情况下确定数据块的起始区域的装置。 提供了用于检测数据字符中的循环移位的其它装置，其在正常条件下即使出现错误也将显示为可接受的代码字。

公开(公告)号：US3587042A

公开(公告)日：1971-06-22

申请号：US3587042D

申请日：1969-07-03

Applicant: GEN ELECTRIC

Inventor： MITCHELL MICHAEL E

IPC: H03M13/43 ,  H04L1/00 ,  G08C25/00 ,  H04L1/10

CPC classification number: H04L1/0057 ,  H03M13/43

Abstract: An improved error correcting coding and decoding system for reliable data transmission. During a first subcycle of decoder operation, estimator logic circuitry generates successive sets of estimator function bits from selected bits of a received code word, and a decision circuit generates successive test bits in accordance with a bit derived from a number of the estimator function bits. A modulo 2 adder compares the successive test bits with the corresponding received bits, and a counter circuit counts the number of disagreements. A disagreement count exceeding a predetermined number indicates that the received code word has become inverted, and circuitry then functions to correct for the inversion by either complementing the received code word before the second decoding subcycle or by complementing the output of the decoding decision circuit during the second subcycle. During the second decoding subcycle, the decision circuit generates successive decoded bits as determined from a majority of the estimator function bits and also from a code word bit if desired. In the event of a ''''tie'''' among the estimator bits, the indeterminate majority decision bit is replaced with the corresponding received bit. The encoding and decoding system may be used either for inversion tolerant coding and decoding of an appropriate code (such as the (21,11) code) or for noninversion tolerant coding and decoding of a related type of code (such as the (21,12) code).

公开(公告)号：US3571795A

公开(公告)日：1971-03-23

申请号：US3571795D

申请日：1969-06-09

Applicant: BELL TELEPHONE LABOR INC

Inventor： TONG SHIH Y

IPC: H03M13/43 ,  H04L1/00 ,  G08C25/00 ,  H04L1/10

CPC classification number: H04L1/0059 ,  H03M13/43

Abstract: Sequences of information, encoded in a self-orthogonal convolution code of rate (b-1)/b and transmitted via a communication channel, are decoded to correct t random errors and bursts of B blocks where each block is b bits in length. The interconnections of the information digit shift registers of the encoder and decoder and their respective parity check digit generating circuits are determined by deriving a difference triangle of order lambda (b-1)t and of size (b-1) (t+1), partitioning the rows of the triangle into b-1 groups of t+1 rows each such that no more than t repetitions of any entry appear in each group, deriving a new difference triangle from each of the b-1 groups by inserting t-2 zeros at the top of the first column of each group and expanding the column into a difference triangle, and reconstructing each new triangle by multiplying each entry by B, and incrementing various entries until each entry of all triangles is different from all other entries of all triangles. The diagonal entries of the resulting triangles determine the interconnections.

公开(公告)号：US3543236A

公开(公告)日：1970-11-24

申请号：US3543236D

申请日：1968-04-10

Applicant: GEN SIGNAL CORP

Inventor： SIBLEY HENRY C

IPC: H04L1/00 ,  H03K13/34 ,  H04L1/10

CPC classification number: H02H3/325

公开(公告)号：US3538497A

公开(公告)日：1970-11-03

申请号：US3538497D

申请日：1967-05-29

Applicant: DATAMAX CORP

Inventor： HARMON SAMUEL T

IPC: G06F17/15 ,  H03M13/39 ,  H04L1/00 ,  H04Q3/02 ,  G08C25/00 ,  H04L1/10

CPC classification number: H04L1/0054 ,  H03M13/39 ,  H04L1/0059

公开(公告)号：US3529289A

公开(公告)日：1970-09-15

申请号：US3529289D

申请日：1965-11-16

Applicant: KNEISEL OTTO ,  EDMUND PTACNIK ,  KARL ANTON LUTZ

Inventor： KNEISEL OTTO ,  PTACNIK EDMUND ,  LUTZ KARL-ANTON

IPC: G11C21/00 ,  H04Q11/04 ,  H04L3/02 ,  H04L1/10

CPC classification number: H04Q11/04 ,  G11C21/00

公开(公告)号：US3496536A

公开(公告)日：1970-02-17

申请号：US3496536D

申请日：1966-05-02

Applicant: XEROX CORP

Inventor： WHEELER JOHN L ,  TOWNSEND STEPHEN E

IPC: H04L1/20 ,  H04L25/04 ,  H04L7/02 ,  H04L1/10

CPC classification number: H04L1/205

公开(公告)号：US06959065B2

公开(公告)日：2005-10-25

申请号：US09839510

申请日：2001-04-20

Applicant: Erik Sparrman ,  Stefan Parkvall ,  Alex Murillo Barrera

Inventor： Erik Sparrman ,  Stefan Parkvall ,  Alex Murillo Barrera

IPC: H04B1/7107 ,  H03K5/01 ,  H03D1/04 ,  H03D1/06 ,  H03K6/04 ,  H04B1/10 ,  H04L1/10

CPC classification number: H04B1/7107 ,  H04B2201/7071

Abstract: A system, method and apparatus for demodulating a received signal using a configurable receiver. The receiver performs the demodulation of a signal according to a selected interference cancellation demodulation scheme. The same receiver can be configured, by setting certain parameters, to behave as a successive interference cancellation (SIC) scheme receiver, a parallel interference cancellation (PIC) scheme receiver, or a hybrid interference cancellation (HIC) scheme receiver. In another aspect of the present invention, the receiver performs its demodulation operation using a single interference cancellation unit (ICU). In addition, the ICU's despreading and respreading functions may be performed by the same processing element.

Abstract translation: 一种使用可配置接收机解调接收信号的系统，方法和装置。 接收机根据选择的干扰消除解调方案执行信号的解调。 可以通过设置某些参数来配置相同的接收机，以表现为连续干扰消除（SIC）方案接收机，并行干扰消除（PIC）方案接收机或混合干扰消除（HIC）方案接收机。 在本发明的另一方面，接收机使用单个干扰消除单元（ICU）来执行其解调操作。 此外，ICU的解扩和重新发送功能可以由相同的处理元件执行。

公开(公告)号：US4451922A

公开(公告)日：1984-05-29

申请号：US332706

申请日：1981-12-21

Applicant: Ziba T. Dearden ,  Yogi K. Puri

Inventor： Ziba T. Dearden ,  Yogi K. Puri

IPC: G06F11/10 ,  H03M13/00 ,  H04L1/10

CPC classification number: G06F11/10

Abstract: An FET transmission logic parity circuit is disclosed which determines the odd or even status of register bits using zero DC current transmission logic. The circuit has a first two FET devices which propagate the state of the preceding odd or even nodes and the corresponding register bit is logically a zero. A second pair of FET devices switch the state of the odd or even nodes when the corresponding register bit is logically a one. In this manner, the output nodes are statically conditioned to either a first potential or a second potential, depending upon the register bit states and no DC current flows between the first and second potential.

Abstract translation: 公开了一种FET传输逻辑奇偶校验电路，其使用零直流电流传输逻辑来确定寄存器位的奇数或偶数状态。 该电路具有前两个FET器件，其传播前一个奇数或偶数节点的状态，相应的寄存器位在逻辑上为零。 第二对FET器件在对应的寄存器位在逻辑上为一个时切换奇数或偶数节点的状态。 以这种方式，根据寄存器位状态，输出节点被静态地调节到第一电位或第二电位，并且没有直流电流在第一和第二电位之间流动。