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公开(公告)号：US11889770B2
公开(公告)日：2024-01-30
申请号：US16850862
申请日：2020-04-16
Applicant: International Business Machines Corporation
Inventor： Salvatore Bernardo Olivadese , Sarunya Bangsaruntip , Daniela Florentina Bogorin , Nicholas Torleiv Bronn , Sean Hart , Patryk Gumann
IPC: H01L39/02 , H10N60/80 , G06N10/00 , H01P3/02 , H10N60/01 , G06N10/40 , H01P11/00 , H01P3/00 , B82Y10/00
CPC classification number: H10N60/80 , G06N10/00 , H01P3/026 , H10N60/01 , B82Y10/00 , G06N10/40 , H01P3/003 , H01P11/003
Abstract: Techniques for designing and fabricating quantum circuitry, including a coplanar waveguide (CPW), for quantum applications are presented. With regard to a CPW, a central conductor and two return conductor lines can be formed on a dielectric substrate, with one return conductor line on each side of the central conductor and separated from it by a space. The central conductor can have bridge portions that can be raised a desired distance above the substrate and base conductor portions situated between the bridge portions and in contact with the surface of the substrate; and/or portions of the substrate underneath the bridge portions of the central conductor can be removed such that the bridge portions, whether raised or unraised, can be the desired distance above the surface of the remaining substrate, and the base conductor portions can be in contact with other portions of the surface of the substrate that were not removed.
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公开(公告)号：US11877523B2
公开(公告)日：2024-01-16
申请号：US17369732
申请日：2021-07-07
Applicant: Microsoft Technology Licensing, LLC
Inventor： Roman Lutchyn , Michael Freedman , Andrey Antipov
IPC: H01L29/20 , H10N60/84 , H03K3/38 , G06N10/00 , B82Y10/00 , H01L29/66 , H01L29/06 , H10N60/01 , H10N60/30 , H10N60/85 , H10N60/10
CPC classification number: H10N60/84 , B82Y10/00 , G06N10/00 , H01L29/0673 , H01L29/66977 , H03K3/38 , H10N60/01 , H10N60/128 , H10N60/30 , H10N60/85 , H01L29/20
Abstract: Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.
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公开(公告)号：US11721462B2
公开(公告)日：2023-08-08
申请号：US16480455
申请日：2018-01-26
Inventor： Thomas Andrew Painter
IPC: H01F6/06 , H01F41/061 , H01F41/04 , H10N60/01
CPC classification number: H01F6/06 , H01F41/048 , H01F41/061 , H10N60/01
Abstract: A high temperature superconductor (HTS) cable comprising at least one coil form comprising a helical channel formed on an exterior surface of the coil form and the helical channel extending at least partially along an axial length of the coil form and a plurality of high temperature superconductor (HTS) tape layers positioned within the helical channel of the coil form. A method for operating a winding machine to produce a high temperature superconductor (HTS) cable comprising a plurality of coil forms comprising a helical channel formed on an exterior surface of the coil form.
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公开(公告)号：US20230247918A1
公开(公告)日：2023-08-03
申请号：US18054488
申请日：2022-11-10
Applicant: Microsoft Technology Licensing, LLC
Inventor： Peter Krogstrup Jeppesen
CPC classification number: H10N69/00 , C23C14/28 , C30B11/12 , C30B23/06 , H01L29/0669 , H10N60/0884 , H10N60/01 , H10N60/10 , H10N60/82 , H10N60/0801 , B82Y10/00
Abstract: A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.
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公开(公告)号：US20230240154A1
公开(公告)日：2023-07-27
申请号：US18010283
申请日：2021-06-22
Applicant: D-WAVE SYSTEMS INC.
Inventor： Byong Hyop Oh , Eric G. Ladizinsky , J. Jason Yao
Abstract: Methods of forming superconducting integrated circuits are discussed. The method includes depositing a first superconducting metal layer to overlie at least a portion of a substrate, depositing a dielectric layer to cover a first region of the first superconducting metal layer, pattering the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and form an opening, and depositing a second superconducting metal layer at an ambient temperature that is less than a melting temperature of the second superconducting metal layer such that the second superconducting metal layer fills the opening and conductively contacts the at least a portion of the first region of the first superconducting metal layer.
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Patent Agency Ranking
公开(公告)号：US11711983B2
公开(公告)日：2023-07-25
申请号：US17975465
申请日：2022-10-27
Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
Inventor： Joseph C. Prestigiacomo , Raymond C. Y. Auyeung , Michael S. Osofsky
IPC: H01L39/24 , H10N60/20 , H10N60/01 , B23K1/00 , B23K3/06 , B23K35/02 , H01L21/67 , H01L21/68 , H01L21/683 , H01L23/00 , B23K101/42 , B23K35/26
CPC classification number: H10N60/203 , B23K1/0016 , B23K3/0623 , B23K35/0222 , H01L21/67092 , H01L21/681 , H01L21/6836 , H01L21/6838 , H01L24/03 , H10N60/01 , H10N60/0801 , B23K35/264 , B23K2101/42 , H01L2221/68309 , H01L2224/03003 , H01L2224/0311 , H01L2224/05109 , H01L2224/05113 , H01L2924/014 , H01L2924/01322
Abstract: This disclosure teaches methods for making high-temperature superconducting striated tape combinations and the product high-temperature superconducting striated tape combinations. This disclosure describes an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure. This invention aligns a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other. The insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections. The ability of this method to precisely align separate tapes to form a single tape structure makes it compatible with a reel-to-reel production process.
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公开(公告)号：US20230227996A1
公开(公告)日：2023-07-20
申请号：US17996369
申请日：2020-04-22
Applicant: Microsoft Technology Licensing, LLC
Abstract: A method comprising: forming a first mask over a substrate; forming one or more shadow walls in the openings of the first mask by selective area growth; forming a second mask over the substrate and shadow walls; forming a second material in the openings of the second mask by selective area growth; and depositing a layer of deposition material by angled deposition over parts of the substrate, shadow walls and second material, whereby regions shadowed by the shadow walls are left uncoated. In embodiments the second material may be a semiconductor and the deposition material may be a superconductor, and the method may be used to form one or more semiconductor-superconductor nanowires for inducing majorana zero modes as part of a quantum computing device.
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公开(公告)号：US20230147168A1
公开(公告)日：2023-05-11
申请号：US17907530
申请日：2020-03-31
Applicant: Microsoft Technology Licensing, LLC
Abstract: One aspect provides semiconductor-superconductor hybrid device comprises a substrate, a first semiconductor component arranged on the substrate, a superconductor component arranged to be capable of energy level hybridisation with the first semiconductor component, and a second semiconductor component arranged as a gate electrode for gating the first semiconductor component. Another aspect provides a semiconductor-superconductor hybrid device, comprising: a substrate; a semiconductor component arranged on the substrate; a gate electrode for gating the semiconductor component; and a superconductor component capable of undergoing energy level hybridisation with the semiconductor component; wherein the gate electrode is arranged in a channel in the substrate. Also provided are methods of fabricating the semiconductor-superconductor hybrid devices.
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公开(公告)号：US20240315148A1
公开(公告)日：2024-09-19
申请号：US18673084
申请日：2024-05-23
Applicant: Microsoft Technology Licensing, LLC
Inventor： Geoffrey Charles Gardner , Asbjørn Cennet Cliff Drachmann , Charles Masamed Marcus , Michael James Manfra
CPC classification number: H10N60/01 , H10N60/0156 , H10N60/0912 , H10N60/10 , H10N60/12 , H10N60/805 , H10N60/85 , H10N60/128
Abstract: A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.
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公开(公告)号：US20240298550A1
公开(公告)日：2024-09-05
申请号：US18661609
申请日：2024-05-11
Applicant: Microsoft Technology Licensing, LLC
Inventor： Quang Thanh TRAN , Judith Cutaran AARTS , John S. HICKMAN , Thanh Cong DINH
CPC classification number: H10N60/01 , G06N10/00 , H01L21/67034 , H10N69/00
Abstract: Techniques are described herein that are capable of progressively thermally drying a quantum circuit. An inert gas is progressively heated by a heater element to provide a heated inert gas. Heated ambient air and the heated inert gas combine in a heating channel, causing a combination of the heated ambient air and the heated inert gas to flow into a probe compartment to progressively thermally dry a quantum circuit therein. A flow rate of the inert gas is controlled to cause the combination to have a relative humidity less than or equal to a threshold. A temperature of the heater element may be controlled to be approximately equal to a progressively increasing target temperature within a tolerance of 3.0° C. Heating of the inert gas may be initiated based on detection of the inert gas, and the flow and heating of the inert gas may be automatically discontinued.
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